Figure 15. Protocol for Serial Data Write wit" />
參數(shù)資料
型號: AS8530A-ASOT
廠商: ams
文件頁數(shù): 18/33頁
文件大?。?/td> 0K
描述: IC SYSTEM BASIS CHIP 8-SOIC
標(biāo)準(zhǔn)包裝: 2,500
系列: *
Revision 1.1
24 - 32
AS8530
Datasheet - Application In form atio n
Figure 15. Protocol for Serial Data Write with Length = 4
Read Command. For Read command RD/WR=1.
After the command code, length of the transfer is send in next two bits, the address of register to be read has to be provided from the MSB to the
LSB. Then one, two, four or eight data bytes can be transferred from the SPI slave to the master, always from the MSB to the LSB.
Each bit of the command and address sections of the frame have to be driven by the 2-Wire SP master on the SP clock (EN pin) positive edge
and the 2-Wire SP slave (device) samples this bit on the next SP clock (EN pin) negative edge. Each bit of the data phase of the frame has to be
driven by the 2-Wire SP slave (device) on the SP clock (EN pin) positive edge and the 2-Wire SP master samples this bit on the next SP clock
(EN pin) negative edge. The following figures illustrate two examples of read command (without and with address self-increment.)
Figure 16. Protocol for Serial Data Read with Length = 1
EN
TX
1
LEN1 LEN0
A
4
A
0
A
1
A
2
A
3
D
0
D
1
D
2
D
3
D
4
D
5
D
7
D
6
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
7
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
Data D7-D0 is
moved to Address
A4-A0 here
10
Command & Address
Phase
Data1 Phase
Data2 Phase
Data3 Phase
Data4 Phase
LEN1 = 1 LEN0 = 0
Length = 4
Data D7-D0 is
moved to Address
A4-A0 + 1 here
Data D7-D0 is
moved to Address
A4-A0 + 2 here
Data D7-D0 is
moved to Address
A4-A0 + 3 here
EN
TX
0 LEN1 LEN0
A4
A0
A1
A2
A3
D0
D1
D2
D3
D4
D5
D7
D6
Transfer edge
Sampling edge
Data D7 – D0 at
address A4 ..A0 is
read here
LEN1 = 0 LEN0 = 0
Command & Address Phase
Data Phase
Length of Transaction = 1
Transfer edge
Sampling edge
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