參數(shù)資料
型號: AS5510-DWLT
廠商: ams
文件頁數(shù): 13/19頁
文件大?。?/td> 248K
描述: IC ENCODER MAGNETIC LIN 6-WLCSP
標準包裝: 12,000
傳感范圍: ±50mT
類型: 線性
電源電壓: 2.5 V ~ 3.6 V
電流 - 電源: 3.5mA
電流 - 輸出(最大): 20mA
輸出類型: 數(shù)字式,開漏極
工作溫度: -30°C ~ 85°C
封裝/外殼: *
供應商設備封裝: *
包裝: *
www.ams.com/AS5510
Revision 0.1
12 - 18
AS5510
Datasheet - Detailed Description
Figure 9. Data Read (Write Pointer, Then Read) - Slave Receive and Transmit
Automatic increment of address pointer. The AS5510 slave automatically increments the address pointer after each byte transferred. 
The increase of the address pointer is independent from the address being valid or not.
Invalid Addresses. If the user sets the address pointer to an invalid address, the address byte is not acknowledged. Nevertheless a read or 
write cycle is possible. The address pointer is increased after each byte.
Reading. When reading from a wrong address, the AS5510 slave returns all zero. The address pointer is increased after each byte. Sequential 
read over the whole address range is possible including address overflow.
Write. A write to a wrong address is not acknowledged by the AS5510 slave, although the address pointer is increased. When the address 
pointer points to a valid address again, a successful write accessed is acknowledged. Page write over the whole address range is possible
including address overflow.
7.4 SDA, SCL Input Filters
Input filters for SDA and SCL inputs are included to suppress noise spikes of less than 50ns. Furthermore the SDA line is delayed by 120ns to
provide an internal hold time for Start/Stop detection to bridge the undefined region of the falling edge of SCL. The delay needs to be smaller
than t
HD.STA
 260ns. For Standard-mode and Fast-mode an internal hold time of 300ns is required, which is not covered by the AS5510 slave.
7.5 Register Map and Description
Table 8. Register Map
Register Address
Bit
Access
Type
7
6
5
4
3
2
1
0
00h
D7
D6
D5
D4
D3
D2
D1
D0
R
01h
OCF
Parity (even)
D9
D8
R
02h
Fast(0)
Slow mode (1)
Polarity(0)
PD(0)
R/W
03h
Offs7
Offs6
Offs5
Offs4
Offs3
Offs2
Offs1
Offs0
R/W
04h
Offs9
Offs8
R/W
05h
Reserved for factory testing
R/W
06h
07h
0Bh
Sens 1
Sens 0
R/W
S
1010110
0
A
XXXXXXXX
A
1010110
1
XXXXXXXX
A
S  Start
SA  Repeated Start
A  Acknowledge (ACK)
Data transferred: X+1 Bytes + Acknowledge
NA  Not Acknowledge (NACK)
Note: Last data byte is followed by NACK
P  Stop
P
<Slave address>
<Word Address (n)>
<Slave Address>
<Data(n+1)>
XXXXXXXX
A
<Data(n)>
Sr
A
XXXXXXXX
NA
<Data(n+X)>
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