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參數資料
| 型號： | AS3510-T |
| 廠商： | ams |
| 文件頁數： | 8/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC AFE ANALOG 49-CABGA |
| 標準包裝： | 2,250 |
| 類型： | 音頻編解碼器 |
| 應用： | 便攜式音頻，電話 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 49-WFBGA |
| 供應商設備封裝： | 49-CSBGA（7x7） |
| 包裝： | 帶卷 (TR) |
Product Brief AS3510
Rev. 1v2, June 2004
CONFIDENTIAL
Page 15 of 19
Pin Configuration for CABGA 49
Ball#
BallName
Type
Function
F1
DVSS
Supply
Neg. supply of digital circuit
B2
PVDD
Supply
Supply of peripheral levelshifter of digital inputs
A2
DVDD
Supply
Pos. supply of digital circuits
G1
MCLK
Din with pull down
Master clock 128*FS / left open - enables PLL
D2
LRCK
Din with pull down
I2S_Left/Right FrameClock = FS
E2
SCLK
Din with pull down
I2S_Serial data clock >=38*FS
F2
SDI
Din with pull down
I2S_Serial data 18bit left oriented, first bit fix L
G2
CSCL
Din stt + spike supr
I2Ccomp_Serial clock to access control register
G3
CSDA
Di/od stt + spike supr
I2Ccomp_Serial data to access control register
F3
SDO
Dout_2mA
I2S_Serial data 14bit left orieted, first bit fix L
E3
USBon
Dout_2mA
USB_indication of usb supply present
G4
RCV
Dout_2mA
USB_differential receiver output
F4
VP
Dout_2mA
USB_signle ended pos. receiver output
E4
VM
Dout_2mA
USB_signle ended neg. receiver output
E5
VPO
Din with pull down
USB_transmitter pos. input
F5
VMO
Din with pull down
USB_transmitter neg. input
D5
OEN
Din with pull up
USB_transmitter output enable (low active)
G5
DVSS
Supply
Neg. supply of digital circuit
G6
DP
Di/o with 1uA pd
USB_pos. I/O terminal
G7
DM
Di/o with 1uA pd
USB_neg. I/O terminal
F6
VTRM
Aout/Supply
USB_3.2V termination voltage regulator output
F7
UVDD
Supply
USB_external supply 4-5.5V
D7
AUX_R
Ain 40/200k to BGND
Analog aux input to audio amp Right channel
D6
AUX_L
Ain 40/200k to BGND
Analog aux input to audio amp Left channel
E7
PWRUP
Din 360k pull down
Enable LDO1 and 2 and DCDC
E6
PLDO3
Din_5state
Selects one of 5 LDO3 states (L, 150kpd open, 150kpu, H)
C7
MICP
Ain 15k to agnd
Microphone pos. input (MIC-ADC path)
C6
MICN
Ain 15k to agnd
Microphone neg. input (MIC-ADC path)
C5
VREF
Ai/o 10uF decpl
Reference voltage of DAC (AVDD)
B6
AGND
Ai/o 10uF decpl
Reference voltage of DAC (AVDD/2)
B7
AVSS
Supply
Neg. supply terminal of analog circuit
A7
AVDD
Aout/Supply
Pos. supply of analog circuits, LDO1 output – 2.9V
A6
BGND
Ai/o 100nF decp
Reference voltage of power-amp (BVDD/2)
B5
BVDD
Supply
Battery supply 3-5.5V
A5
OUTR
Aout
Speaker/Headphone output (4 ohm min.)
A4, B4
BVSS
Supply
Neg. supply terminal of Power Amp.
A3
OUTL
Aout
Speaker/Headphone output (4 ohm min.)
B3
BVDD
Supply
Battery supply 3-5.5V
A1
VSSDCDC
Supply
Power Ground for DCDC Converter
B1
VSSDCDC
Supply
Power Ground for DCDC Converter
C1
SWDCDC
Aout
Switch Output for DCDC Converter
D1
SWDCDC
Aout
Switch Output for DCDC Converter
E1
VB1V
Supply
Battery Supply Input (1V-3V)
C2
n.c.
not connected
C3
n.c.
not connected
C4
n.c.
not connected
D4
n.c.
not connected
Table 19
Table of Pin Configuration for CABGA 49
ams
AG
Technical
content
still
valid
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