參數(shù)資料
型號： APMOTOR56F8000E
廠商： Freescale Semiconductor
文件頁數(shù)： 94/124頁
文件大小： 0K
描述： KIT DEMO MOTOR CTRL SYSTEM
標(biāo)準(zhǔn)包裝： 1
附件類型： 電機控制器
適用于相關(guān)產(chǎn)品： DEMO56F8013，DEMO56F8013-E
相關(guān)產(chǎn)品： MC56F8006VWL-ND - DSC 16K FLASH 32MHZ 28-SOIC
MC56F8006VLF-ND - DSC 16K FLASH 32MHZ 48-LQFP
MC56F8006VLC-ND - DSC 16K FLASH 32MHZ 32-LQFP
MC56F8002VWL-ND - DSC 12K FLASH 32MHZ 28-SOIC
DEMO56F8014-E-ND - BOARD DEMO MC56F8014 W/UNIV PS
DEMO56F8014-ND - BOARD DEMO MC56F8014 W/US PS
DEMO56F8014-EE-ND - BOARD DEMO FOR 56F8014
DEMO56F8013-EE-ND - BOARD DEMO FOR 56F8013
MC56F8014VFAE-ND - IC DIGITAL SIGNAL CTRLR 32-LQFP
MC56F8013VFAE-ND - IC DIGITAL SIGNAL CTLR 32-LQFP
更多...
Register Descriptions
56F8014 Technical Data, Rev. 11
Freescale Semiconductor
71
01101 = Reserved for factory test—Continuous peripheral clock
01110 = Reserved for factory test—Continuous inverted peripheral clock
01111 = Reserved for factory test—Continuous high-speed peripheral clock
6.3.8
SIM GPIO Peripheral Select Register (SIM_GPS)
All of the peripheral pins on the 56F8014 share their Input/Output (I/O) with GPIO ports. To select
peripheral or GPIO control, program the corresponding bit in the GPIOx_PEREN register in the GPIO
module. (See MC56F8000RM, the 56F801x Peripheral Reference Manual, for details.) In some cases,
there are two possible peripherals as well as the GPIO functionality available for control of the I/O. In these
cases, the SIM_GPS register is used to determine which peripheral has control when the corresponding
I/O pin is configured in peripheral mode.
As shown in Figure 6-9, the GPIO Peripheral Enable Register (PEREN) has the final control over which
pin controls the I/O. SIM_GPS simply decides which peripheral will be routed to the I/O when
PEREN = 1.
Figure 6-9 Overall Control of Pads Using SIM_GPS Control
Figure 6-10 GPIO Peripheral Select Register (SIM_GPS)
6.3.8.1
Quad Timer Clock Rate (TCR)—Bit 15
This bit selects the clock speed for the Quad Timer module.
0 = Quad Timer module clock rate equals system clock rate, to a maximum 32 MHz (default)
1 = Quad Timer module clock rate equals three times sytem clock rate, to a maximum 96 MHz
Base + $B
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
TCR
PCR
0
CFG_
B7
CFG_
B6
CFG_
B5
CFG_
B4
CFG_
B3
CFG_
B2
CFG_
B1
CFG_
B0
CFG_A5
CFG_A4
Write
RESET
0
00000000
0000
GPIOB_PEREN Register
GPIO Controlled
I/O Pad Control
SIM_GPS Register
Quad Timer Controlled
SCI Controlled
0
1
0
1
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