- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄16900 > APMOTOR56F8000E (Freescale Semiconductor)KIT DEMO MOTOR CTRL SYSTEM PDF資料下載
參數(shù)資料
| 型號(hào)： | APMOTOR56F8000E |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 100/124頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEMO MOTOR CTRL SYSTEM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 附件類型： | 電機(jī)控制器 |
| 適用于相關(guān)產(chǎn)品： | DEMO56F8013，DEMO56F8013-E |
| 相關(guān)產(chǎn)品： | MC56F8006VWL-ND - DSC 16K FLASH 32MHZ 28-SOIC MC56F8006VLF-ND - DSC 16K FLASH 32MHZ 48-LQFP MC56F8006VLC-ND - DSC 16K FLASH 32MHZ 32-LQFP MC56F8002VWL-ND - DSC 12K FLASH 32MHZ 28-SOIC DEMO56F8014-E-ND - BOARD DEMO MC56F8014 W/UNIV PS DEMO56F8014-ND - BOARD DEMO MC56F8014 W/US PS DEMO56F8014-EE-ND - BOARD DEMO FOR 56F8014 DEMO56F8013-EE-ND - BOARD DEMO FOR 56F8013 MC56F8014VFAE-ND - IC DIGITAL SIGNAL CTRLR 32-LQFP MC56F8013VFAE-ND - IC DIGITAL SIGNAL CTLR 32-LQFP 更多... |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)當(dāng)前第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)
Clock Generation Overview
56F8014 Technical Data, Rev. 11
Freescale Semiconductor
77
Figure 6-14 I/O Short Address Location Low Register (SIM_IOSALO)
6.3.10.3
Input/Output Short Address Location (ISAL[21:6])—Bit 15–0
This field represents the lower 16 address bits of the “hard coded” I/O short address.
6.4 Clock Generation Overview
The SIM uses master clocks, 2X system clock at a maximum of 64 MHz, from the OCCS module to
produce the peripheral and system (core and memory) clocks at a maximum of 32 MHz. It divides the
master clock by two and gates it with appropriate power mode and clock gating controls. The high speed
peripheral clock input from OCCS operates at three times the system clock for PWM and Quad Timer
module at a maximum of 96 MHz.
The OCCS configuration controls the operating frequency of the SIM’s master clocks. In the OCCS, either
an external clock or the relaxation oscillator can be selected as the master clock source (MSTR_OSC).
When selected, the relaxation oscillator can be operated at full speed (8 MHz), standby speed (200 kHz),
or powered down. An 8 MHz clock can be multiplied to 192 MHz using the PLL and postscaled to provide
a variety of high speed clock rates. Either the postscaled PLL output or the input clock of the PLL signal
can be selected to produce the master clocks to the SIM. When the PLL is not selected, the high speed
peripheral clock is disabled and the 2x system clock is the input clock from either the internal relaxation
oscillator or from an external clock source.
In combination with the OCCS module, the SIM provides power modes (see Section 6.5), clock enables
(SIM_PCE register, CLK_DIS, ONCE_EBL), and clock rate controls (TCR, PCR) to provide flexible
control of clocking and power utilization. The SIM’s clock enable controls can be used to disable
individual clocks when not needed. The clock rate controls enable the high speed clocking option for the
Timer channels and PWM but require the PLL to be on and selected. Refer to the 56F801X Peripheral
Reference Manual for further details.
6.5 Power-Down Modes
The 56F8014 operates in one of five Power-Down modes, as shown in Table 6-3
.
Base + $E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
ISAL[21:6]
Write
RESET
11111
1
Table 6-3 Clock Operation in Power-Down Modes
Mode
Core Clocks
Peripheral Clocks
Description
Run
Core and memory
clocks disabled
Peripheral clocks
enabled
Device is fully functional
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TCMD-05-S-06.00-01 | CABLE ASSEM 2MM 10POS SGL END 6" |
| 8532-09L | INDUCTOR 4.7UH POWER SMD |
| LM4040BEX3-5.0+T | IC VREF SHUNT PREC 5V SC-70-3 |
| GBC13DRAN-S734 | CONN EDGECARD 26POS .100 R/A SLD |
| LM4040BEX3-2.5+T | IC VREF SHUNT PREC 2.5V SC-70-3 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| APMP100 | 功能描述:CHEMICAL METERING PUMP. 制造商:3m 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:1 |
| AP-MP3 | 制造商:Rogue Robotics 功能描述:uMP3 Playback Module 3-5 Volt MP3 PCM WAV Interface with PIC |
| APMR0016 | 功能描述:MOD APMR 3-PH VAULT DET DIN RAIL RoHS:否 類別:工業(yè)控制，儀表 >> 專用 系列:APMR 標(biāo)準(zhǔn)包裝:1 系列:PSE200 產(chǎn)品目錄頁(yè)面:2804 (CN2011-ZH PDF) 其它名稱:606-1016 |
| APMR0086 | 制造商:Red Lion Controls 功能描述:SIGNAL CONDIT MOD, 3 PH FAULT DET 380V 制造商:Red Lion Controls 功能描述:3 PHASE FAULT DETECTOR 380VAC |
| APMR0096 | 制造商:Red Lion Controls 功能描述:Relay, Analog Phase Mod, 480 制造商:Red Lion Controls 功能描述:3 PHASE FAULT DETECTOR 480VAC |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。