ProASICPLUS Flash Family FPGAs v5.9 2-71 Synchronous FIFO Write Note: The plo" />
參數(shù)資料
型號: APA750-FG676I
廠商: Microsemi SoC
文件頁數(shù): 159/178頁
文件大?。?/td> 0K
描述: IC FPGA PROASIC+ 750K 676-FBGA
標準包裝: 40
系列: ProASICPLUS
RAM 位總計: 147456
輸入/輸出數(shù): 454
門數(shù): 750000
電源電壓: 2.3 V ~ 2.7 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 676-BGA
供應商設備封裝: 676-FBGA(27x27)
ProASICPLUS Flash Family FPGAs
v5.9
2-71
Synchronous FIFO Write
Note: The plot shows the normal operation status.
Figure 2-44 Synchronous FIFO Write
Table 2-67 TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/Industrial
TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
Description
Min.
Max.
Units
Notes
CCYC
Cycle time
7.5
ns
CMH
Clock high phase
3.0
ns
CML
Clock low phase
3.0
ns
DCH
DI hold from WCLKS
0.5
ns
DCS
DI setup to WCLKS
1.0
ns
FCBA
New FULL access from WCLKS
3.0*
ns
ECBA
EMPTY
↓ access from WCLKS ↓
3.0*
ns
ECBH,
FCBH,
HCBH
Old EMPTY, FULL, EQTH, & GETH valid hold
time from WCLKS
1.0
ns
Empty/full/thresh are invalid from the end of
hold until the new access is complete
HCBA
EQTH or GETH access from WCLKS
4.5
ns
WPCA
New WPE access from WCLKS
3.0
ns
WPE is invalid, while PARGEN is active
WPCH
Old WPE valid from WCLKS
0.5
ns
WRCH, WBCH WRB & WBLKB hold from WCLKS
0.5
ns
WRCS, WBCS
WRB & WBLKB setup to WCLKS
1.0
ns
Note: * At fast cycles, ECBA and FCBA = MAX (7.5 ns – CMH), 3.0 ns.
WCLKS
WPE
DI
EMPTY
EQTH, GETH
FULL
(Full Inhibits Write)
WRB, WBLKB
Cycle Start
tWRCH, tWBCH
tECBH, tFCBH
tECBA, tFCBA
tHCBA
tWRCS, tWBCS
tDCS
tWPCA
tCMH
tCML
tCCYC
tWPCH
tDCH
tHCBH
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