ProASICPLUS Flash Family FPGAs v5.9 2-41 Table 2-26 AC Specifications (3" />
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鍨嬭櫉(h脿o)锛� APA750-BG456
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 126/178闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA PROASIC+ 750K 456-PBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 24
绯诲垪锛� ProASICPLUS
RAM 浣嶇附瑷�(j矛)锛� 147456
杓稿叆/杓稿嚭鏁�(sh霉)锛� 356
闁€鏁�(sh霉)锛� 750000
闆绘簮闆诲锛� 2.3 V ~ 2.7 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 456-BBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 456-PBGA锛�35x35锛�
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ProASICPLUS Flash Family FPGAs
v5.9
2-41
Table 2-26 AC Specifications (3.3 V PCI Revision 2.2 Operation)
Symbol Parameter
Condition
Commercial/Industrial/Military/MIL-STD- 883
Units
Min.
Max.
IOH(AC)
Switching Current High
0 < VOUT 鈮� 0.3VDDP
*
鈥�12VDDP
mA
0.3VDDP 鈮� VOUT < 0.9VDDP
*
(鈥�17.1 + (VDDP 鈥� VOUT))
mA
0.7VDDP < VOUT < VDDP
*
See equation C 鈥� page 124 of
the PCI Specification
document rev. 2.2
(Test Point)
VOUT = 0.7VDDP
*
鈥�32VDDP
mA
IOL(AC)
Switching Current Low
VDDP > VOUT 鈮� 0.6VDDP
*
16VDDP
mA
0.6VDDP > VOUT > 0.1VDDP
1
(26.7VOUT)mA
0.18VDDP > VOUT > 0
*
See equation D 鈥� page 124 of
the PCI Specification
document rev. 2.2
(Test Point)
VOUT = 0.18VDDP
38VDDP
mA
ICL
Low Clamp Current
鈥�3 < VIN 鈮� 鈥�1
鈥�25 + (VIN + 1)/0.015
mA
ICH
High Clamp Current
VDDP + 4 > VIN 鈮� VDDP + 1
25 + (VIN 鈥� VDDP 鈥� 1)/0.015
mA
slewR
Output Rise Slew Rate
0.2VDDP to 0.6VDDP load
*
14
V/ns
slewF
Output Fall Slew Rate
0.6VDDP to 0.2VDDP load
*
14
V/ns
Note: * Refer to the PCI Specification document rev. 2.2.
Pin
Output
Buffer
1/2 in. maxx
10 pF
1k
Pin
Output
Buffer
10 pF
1k
Pad Loading Applicable to the Rising Edge PCI
Pad Loading Applicable to the Falling Edge PCI
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