ProASICPLUS Flash Family FPGAs v5.9 2-17 Logic Tile Timing Characteristics
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� APA600-FG676I
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 99/178闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA PROASIC+ 600K 676-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 40
绯诲垪锛� ProASICPLUS
RAM 浣嶇附瑷�(j矛)锛� 129024
杓稿叆/杓稿嚭鏁�(sh霉)锛� 454
闁€(m茅n)鏁�(sh霉)锛� 600000
闆绘簮闆诲锛� 2.3 V ~ 2.7 V
瀹夎椤�(l猫i)鍨嬶細 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 676-BGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 676-FBGA锛�27x27锛�
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ProASICPLUS Flash Family FPGAs
v5.9
2-17
Logic Tile Timing Characteristics
Timing characteristics for ProASICPLUS devices fall into
three categories: family dependent, device dependent,
and design dependent. The input and output buffer
characteristics are common to all ProASICPLUS family
members. Internal routing delays are device dependent.
Design dependency means that actual delays are not
determined until after placement and routing of the
user鈥檚 design are complete. Delay values may then be
determined by using the Timer utility or by performing
simulation with post-layout delays.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most
timing-critical paths. Critical nets are determined by net
property assignment prior to place-and-route. Refer to
the Actel Designer User鈥檚 Guide or online help for details
on using constraints.
Timing Derating
Since ProASICPLUS devices are manufactured with a
CMOS process, device performance will vary with
temperature, voltage, and process. Minimum timing
parameters
reflect
maximum
operating
voltage,
minimum operating temperature, and optimal process
variations. Maximum timing parameters reflect minimum
operating voltage, maximum operating temperature,
and
worst-case
process
variations
(within
process
specifications). The derating factors shown in Table 2-9
should be applied to all timing data contained within
this datasheet.
All timing numbers listed in this datasheet represent
sample timing characteristics of ProASICPLUS devices.
Actual timing delay values are design-specific and can be
derived from the Timer tool in Actel鈥檚 Designer software
after place-and-route.
Table 2-9
Temperature and Voltage Derating Factors
(Normalized to Worst-Case Commercial, TJ = 70掳C, VDD = 2.3 V)
鈥�55掳C
鈥�40掳C
0掳C
25掳C
70掳C
85掳C
110掳C
125掳C
135掳C
150掳C
2.3 V
0.84
0.860.910.941.001.021.05
1.13
1.181.27
2.5 V
0.81
0.820.870.900.950.981.01
1.09
1.131.21
2.7 V
0.77
0.790.830.860.910.930.96
1.04
1.081.16
Notes:
1. The user can set the junction temperature in Designer software to be any integer value in the range of 鈥�55掳C to 175掳C.
2. The user can set the core voltage in Designer software to be any value between 1.4 V and 1.6 V.
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