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ProASICPLUS Flash Family FPGAs
2- 44
v5.9
Output Buffer Delays
Figure 2-24 Output Buffer Delays
Table 2-31 Worst-Case Commercial Conditions
VDDP = 3.0 V, VDD = 2.3 V, 35 pF load, TJ = 70掳C
Macro Type
Description
Max. tDLH
1
Max. tDHL
2
Units
Std.
OB33PH
3.3 V, PCI Output Current, High Slew Rate
2.0
2.2
ns
OB33PN
3.3 V, High Output Current, Nominal Slew Rate
2.2
2.9
ns
OB33PL
3.3 V, High Output Current, Low Slew Rate
2.5
3.2
ns
OB33LH
3.3 V, Low Output Current, High Slew Rate
2.6
4.0
ns
OB33LN
3.3 V, Low Output Current, Nominal Slew Rate
2.9
4.3
ns
OB33LL
3.3 V, Low Output Current, Low Slew Rate
3.0
5.6
ns
Notes:
1. tDLH = Data-to-Pad High
2. tDHL = Data-to-Pad Low
Table 2-32 Worst-Case Commercial Conditions
VDDP = 2.3 V, VDD = 2.3 V, 35 pF load, TJ = 70掳C
Macro Type
Description
Max. tDLH
1
Max. tDHL
2
Units
Std.
OB25LPHH
2.5 V, Low Power, High Output Current, High Slew Rate3
2.0
2.1
ns
OB25LPHN
2.5 V, Low Power, High Output Current, Nominal Slew Rate3
2.4
3.0
ns
OB25LPHL
2.5 V, Low Power, High Output Current, Low Slew Rate3
2.9
3.2
ns
OB25LPLH
2.5 V, Low Power, Low Output Current, High Slew Rate3
2.7
4.6
ns
OB25LPLN
2.5 V, Low Power, Low Output Current, Nominal Slew Rate3
3.5
4.2
ns
OB25LPLL
2.5 V, Low Power, Low Output Current, Low Slew Rate3
4.0
5.3
ns
Notes:
1. tDLH = Data-to-Pad High
2. tDHL = Data-to-Pad Low
3. Low-power I/Os work with VDDP = 2.5 V 卤10% only. VDDP = 2.3 V for delays.
Table 2-33 Worst-Case Military Conditions
VDDP = 3.0V, VDD = 2.3V, 35 pF load, TJ = 125掳C for Military/MIL-STD-883
Macro Type
Description
Max.
tDLH
1
Max.
tDHL
2
Units
Std.
OB33PH
3.3V, PCI Output Current, High Slew Rate
2.1
2.3
ns
OB33PN
3.3V, High Output Current, Nominal Slew Rate
2.5
3.2
ns
PAD
A
50%
PAD
VOL
V
OH
50%
t
DLH
50%
t
DHL
35 pF
A
OBx
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