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鍨嬭櫉锛� APA075-TQG100
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ProASICPLUS Flash Family FPGAs
v5.9
2-43
Table 2-29 Worst-Case Military Conditions
VDDP = 3.0 V, VDD = 2.3 V, 35 pF load, TJ = 125掳C for Military/MIL-STD-883
Macro Type
Description
Max.
tDLH
1
Max.
tDHL
2
Max.
tENZH
3
Max.
tENZL
4
Units
Std.
OTB33PH
3.3 V, PCI Output Current, High Slew Rate
2.2
2.4
2.3
2.1
ns
OTB33PN
3.3 V, High Output Current, Nominal Slew Rate
2.4
3.2
2.7
2.3
ns
OTB33PL
3.3 V, High Output Current, Low Slew Rate
2.7
3.5
2.9
3.0
ns
OTB33LH
3.3 V, Low Output Current, High Slew Rate
2.7
4.3
3.0
3.1
ns
OTB33LN
3.3 V, Low Output Current, Nominal Slew Rate
3.3
4.7
3.4
4.4
ns
OTB33LL
3.3 V, Low Output Current, Low Slew Rate
3.2
6.0
3.5
5.9
ns
Notes:
1. tDLH = Data-to-Pad High
2. tDHL = Data-to-Pad Low
3. tENZH = Enable-to-Pad, Z to High
4. tENZL = Enable-to-Pad, Z to Low
Table 2-30 Worst-Case Military Conditions
VDDP = 2.3 V, VDD = 2.3 V, 35 pF load, TJ = 125掳C for Military/MIL-STD-883
Macro Type
Description
Max.
tDLH
1
Max.
tDHL
2
Max.
tENZH
3
Max.
tENZL
4
Units
Std.
OTB25LPHH
2.5 V, Low Power, High Output Current, High Slew Rate5
2.3
2.4
2.1
ns
OTB25LPHN
2.5 V, Low Power, High Output Current, Nominal Slew
Rate5
2.7
3.2
2.8
2.1
ns
OTB25LPHL
2.5 V, Low Power, High Output Current, Low Slew Rate5
3.2
3.5
3.3
2.8
ns
OTB25LPLH
2.5 V, Low Power, Low Output Current, High Slew Rate5
3.0
5.0
3.2
2.8
ns
OTB25LPLN
2.5 V, Low Power, Low Output Current, Nominal Slew Rate5
3.7
4.5
4.1
ns
OTB25LPLL
2.5 V, Low Power, Low Output Current, Low Slew Rate5
4.4
5.8
4.4
5.4
ns
Notes:
1. tDLH = Data-to-Pad High
2. tDHL = Data-to-Pad Low
3. tENZH = Enable-to-Pad, Z to High
4. tENZL = Enable-to-Pad, Z to Low
5. Low power I/O work with VDDP = 2.5 V 卤 10% only. VDDP = 2.3 V for delays.
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