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參數(shù)資料
| 型號： | AN105 |
| 廠商： | Vishay Intertechnology,Inc. |
| 英文描述： | FETS AS VOLTAGE-CONTROLLED RESISTORS |
| 中文描述： | 場效應(yīng)管的電壓，控制電阻 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 106K |
| 代理商： | AN105 |
AN105
2
Siliconix
10-Mar-97
–400
–200
200
V
DS
(mV)
400
V
GS
= –3.0 V
200
0 V
–1.5 V
D
G
S
I
D
V
GS
= 0 V
–1.5 V
–2.5 V
(
I
D
A
V
DS
(V)
(
I
D
3
2
1
5
10
–3.0 V
0 V
–1.5 V
#
–2.5 V
–2.5 V
V
GS
= –3.0 V
–200
The graph in Figure 3 is useful in estimating r
DS
values
at any given value of V
GS
. The resistance is normalized
to its specific value at V
GS
= 0 V. The dynamic range of
r
DS
is shown as greater than 100:1, although for best con-
trol of r
DS
a range of 10:1 is normally used.
Figure 3.
Normalized r
DS
Data
/
D
r
D
(
)
V
GS
/V
GS(off)
0
0.2
0.4
0.6
0.8
1.0
1
10
100
1000
V
DS
0.1 V
r
DS
r
DS(on)
1 – V
GS
V
GS(off)
Siliconix offers a family of n-channel FETs specifically
intended for use as voltage-controlled resistors. These de-
vices have r
DS(on)
values ranging from 20 to 4,000 ,
where VCR2N = 20 – 60 , VCR4N = 200 – 600 ,
VCR7N = 4 k – 8 k .
Applications for VCRs
A simple application of a FET VCR is shown in Figure 4,
the circuit for a voltage divider attenuator.
V
OUT
V
IN
VCR
V
GS
R
+
–
Figure 4.
Simple Attenuator Circuit
!
V
OUT
V
IN
r
DS
R
r
DS
(1)
It is assumed that the output voltage is not so large as to
push the VCR out of the linear resistance region, and that
the r
DS
is not shunted by the load.
" ! " !
V
OUT(min)
V
IN
r
DS(on)
R
r
DS(on
)
(2)
Signal Distortion: Causes
Figure 2 shows that the bias lines bend down as V
DS
increases in a positive direction toward the pinch-off voltage
of the FET. The bending of the bias lines results in a change
in r
DS
, and hence the distortion encountered in VCR circuits;
note that the distortion occurs in both the first and third
quadrants. Distortion results because the channel depletion
layer increases as V
DS
reduces the drain current so that a
pinch-off condition is reached when V
DS
= V
GS
– V
GS(off)
.
Figure 5 shows how the current has an opposite effect in the
third quadrant, increasing negatively with an increasingly
negative V
DS
. This is due to the forward conduction of the
gate-to-channel junction when the drain signal exceeds the
negative gate bias voltage.
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