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參數(shù)資料
| 型號： | AN105 |
| 廠商： | Vishay Intertechnology,Inc. |
| 英文描述： | FETS AS VOLTAGE-CONTROLLED RESISTORS |
| 中文描述： | 場效應(yīng)管的電壓，控制電阻 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 106K |
| 代理商： | AN105 |
AN105
Siliconix
10-Mar-97
1
Introduction: The Nature of VCRs
A voltage-controlled resistor (VCR) may be defined as a
three-terminal variable resistor where the resistance val-
ue between two of the terminals is controlled by a voltage
potential applied to the third.
For a junction field-effect transistor (JFET) under certain
operating conditions, the resistance of the drain-source
channel is a function of the gate-source voltage alone and
the JFET will behave as an almost pure ohmic resistor.
Maximum drain-source current, I
DSS
, and minimum re-
sistance r
DS(on)
, will exist when the gate-source voltage
is equal to zero volts (V
GS
= 0). If the gate voltage is in-
creased (negatively for n-channel JFETs and positively
for p-channel), the resistance will also increase. When the
drain current is reduced to a point where the FET is no
longer conductive, the maximum resistance is reached.
The voltage at this point is referred to as the pinchoff or
cutoff voltage and is symbolized by V
GS
= V
GS(off)
. Thus
the device functions as a voltage- controlled resistor.
Region 1
Region 2
Current Saturation Region
Ohmic Region
→
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"( %" $
"
'! (
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Figure 1 details typical operating characteristics of an n-
channel JFET. Most amplification or switching operations
of FETs occur in the constant-current (saturated) region,
shown as Region II. A close inspection of Region I (the un-
saturated or pre-pinchoff area) reveals that the effective
slope indicative of conductance across the channel from
drain-to-source is different for each value of gate-source
bias voltage. The slope is relatively constant over a range of
applied drain voltages, so long as the gate voltage is also
constant and the drain voltage is low.
Resistance Properties of FETs
The unique resistance-controlling properties of FETs can
be deduced from Figure 2, which is an expanded-scale
plot of the encircled area in the lower left-hand corner of
Figure 1. The output characteristics all pass through the
origin, near which they become almost straight lines so
that the incremental value of channel resistance, r
DS
, is
essentially the same as that of dc resistance, r
DS
, and is a
function of V
GS.
Figure 2 shows an extension of the operating characteris-
tics into the third quadrant for a typical n-channel JFET.
While such devices are normally operated with a positive
drain-source voltage, small negative values of V
DS
are
possible. This is because the gate-channel PN junction
must be slightly forward-biased before any significant
amount of gate current flows. The slope of the V
GS
bias
line is equal to I
D
/V
DS
= 1/r
DS
. This value is controlled
by the amount of voltage applied to the gate. Minimum
r
DS
, usually expressed as r
DS(on)
, occurs at V
GS
= 0 and
is dictated by the geometry of the FET. A device with a
channel of small cross-sectional area will exhibit a high
r
DS(on)
and a low I
DSS
. Thus a FET with high I
DSS
should
be chosen where design requirements indicate the need
for a low r
DS(on)
.
Updates to this app note may be obtained via facsimile by calling Siliconix FaxBack, 1-408-970-5600. Please request FaxBack document #70598.
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