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參數(shù)資料
| 型號(hào)： | AN10145 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Bi-directional low voltage translators |
| 中文描述： | 雙向低電壓轉(zhuǎn)換器 |
| 文件頁數(shù)： | 23/24頁 |
| 文件大?。?/td> | 325K |
| 代理商： | AN10145 |
23
16.
Multi-part Question :
We are using the GTL2000 for the one-way level shifting from 3.3V -> 1.8V.
Question A:
let us know the set up time and the hold time of GTL2000.
Answer A:
"Set up and hold" are usually referring to flip flop or latch parts, so they have no meaning with respect
to the GTL2000 parts.
Question B:
When the transistor is off and the GREF and DREF are Low, it is specified that the input and the
output are don't care. When GTL2000 becomes this state, is this correct that all input and output of the GTL2000
become the high impedance. Please let us know the maximum voltage we can induce to the I/O of GTL2000 when it
is the high impedance. Can we induce the 5.5V max to the I./O
Answer B:
If the GREF pin is at ground the transistors in the GTL2000 are off and the path from each D to its S is
high impedance.
Note
: If the intent is to switch the GREF pin the enable time and the disable time will depend upon how quickly the
GREF pin voltage transitions between ground and the bias voltage for the appropriate level shift conditions.
For example, let assume that the 200 k
pull-up resistor is used to connect the GREF and DREF to the 3.3 V power
supply and a 1
μ
F capacitor is used for decoupling between the GREF and DREF node and ground. The RC time
constant of the GREF node would be 0.2 s meaning that the enable time would be on the order of 0.2 s. The disable
time if the SREF is connected to ground or if the GREF is connected to ground by a transistor or open drain or open
collector gate would be the delay of the gate because the internal time constant is only about 5 ns as soon as the
GREF falls below about 0.5 V the transistors are off.
If the need is for the GTL2000 to enable and disable quickly about the best solution that could be recommended
would be to use a high drive CMOS gate (with a minimum high level drive current maximum of at least 15 mA), a
series 50 ohm resistor between the CMOS gate and the GREF pin of the GTL2000 and a diode with its anode on the
GREF and 50 ohm resistor node and its anode to the 1.8 V power supply. This solution is fast ~ 10 ns at the expense
of wasting about 15 mA of current and doing a less than perfect translation. This will also require pull-up resistors
on the low voltage side as well as the high voltage side because the diode forward does not match the threshold of
the NMOS transistors in the GTL2000. Increasing the 50 ohm resistor if slower enable and disable times can be
tolerated can reduce power.
ADDITIONAL INFORMATION
The latest datasheets for the GTL2000/02/10 Bi-Directional Low Voltage Translators and other Specialty Logic products
can be found at the Philips Semiconductors website:
www.philipslogic.com
Additionnal technical support for GTL2000/02/10 Bi-Directional Low Voltage Translator devices can be provided by e-
mailing the question to:
I2C.support@philips.com
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