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6
Biasing and Operation
The recommended quiescent DC
bias condition for optimum
efficiency, performance, and
reliability is Vd1 = 3.5 volts and
Vd2 = 5 volts with Vgg set for Id1
+ Id2 = 780 mA (no connection
to Vg1). This bias arrangement
results in default quiescent
drain currents Id1 = 280 mA, Id2
= 500 mA. A single DC gate
supply connected to Vgg will
bias all gain stages.
Vd2 at 5 volts is desired, an
additional wire bond connection
from the Vg1 pad to Vgg external
bypass chip capacitor (Shorting
Vg1 to Vgg) will balance the
current in each gain stage. Vgg
(= Vg1) can be adjusted for
Id1+Id2 = 780 mA. Muting can be
accomplished by setting Vg1 and
/or Vgg to the pinch- off voltage
Vp.
An optional output power
detector network is also
provided. Detector sensitivity
can be adjusted by biasing the
diodes with typically 1 to 5
volts applied to the Det- bias
terminal. Simply connecting
Det- Bias to the Vd2 supply is a
convenient method of biasing
this detector network. The
differential voltage between the
Det- Ref and Det- Out pads can
be correlated with the RF power
emerging from the RF output
port. The detected voltage is
given by :
V = (Vref Vdet) - Vofs
Where Vref is the voltage at the
DET_REF port, Vdet is a voltage
at the DET_OUT port, and Vofs
is the zero- input- power offset
voltage. There are three
methods to calculate Vofs:
1) Vofs can be measured before
each detector measurement (by
removing or switching off the
power source and measuring
Vref Vdet). This method gives
an error due to temperature
drift of less than 0.0002 dB/°C.
2) Vofs can be measured at a
single reference temperature.
The drift error will be less than
0.25 dB.
3) Vofs can either be
characterized over temperature
and stored in a lookup table, or
it can be measured at two
temperatures and a linear fit
used to calculate Vofs at any
temperature. This method gives
an error close to method #1.
With reference to Figure 13, the
RF input is DC coupled to a
shunt 50
resistor but it is DC
blocked to the input of the first
stage. The RF output is DC
blocked to the output of the
second stage, however, it is DC
coupled to the detector bias
circuit. If the output detector is
biased using the on- chip
optional Det- Bias network, an
external DC blocking capacitor
may be required at the RF
Output port.
No ground wires are needed
since ground connections are
made with plated through- holes
to the backside of the device.
Assembly Techniques
The backside of the AMMC- 5033
chip is RF ground. For
microstripline applications, the
chip should be attached directly
to the ground plane (e.g., circuit
carrier or heatsink) using
electrically conductive epoxy
[1].
For best performance, the
topside of the MMIC should be
brought up to the same height
as the circuit surrounding it.
This can be accomplished by
mounting a gold plated metal
shim (same length and width as
the MMIC) under the chip,
which is of the correct
thickness to make the chip and
adjacent circuit coplanar.
The amount of epoxy used for
chip and or shim attachment
should be just enough to
provide a thin fillet around the
bottom perimeter of the chip or
shim. The ground plane should
be free of any residue that may
jeopardize electrical or
mechanical attachment.
The location of the RF bond
pads is shown in Figure 14.
Note that all the RF input and
output ports are in a Ground-
Signal- Ground configuration.
RF connections should be kept
as short as reasonable to
minimize performance
degradation due to undesirable
series inductance. A single bond
wire is sufficient for signal
connections, however double-
bonding with 0.7 mil gold wire
or the use of gold mesh
[2] is
recommended for best
performance, especially near the
high end of the frequency range.
Thermosonic wedge bonding is
the preferred method for wire
attachment to the bond pads.
Gold mesh can be attached
using a 2 mil round tracking
tool and a tool force of
approximately 22 grams with an
ultrasonic power of roughly 55
dB for a duration of 76
± 8 mS.
A guided wedge at an ultrasonic
power level of 64 dB can be
used for the 0.7 mil wire.
The
recommended wire bond stage
temperature is 150
± 2°C.
Caution should be taken to not
exceed the Absolute Maximum
Rating for assembly temperature
and time.
The chip is 100
m thick and
should be handled with care.
This MMIC has exposed air
bridges on the top surface and
should be handled by the edges
or with a custom collet (do not
pick up die with vacuum on die
center.)
This MMIC is also static
sensitive and ESD handling
precautions should be taken.
Notes:
1. Ablebond 84-1 LM1 silver epoxy is
recommended.
2. Buckbee-Mears Corporation, St. Paul, MN,
800-262-3824