參數(shù)資料
型號(hào)： AM49PDL127BH
廠商： Spansion Inc.
英文描述： 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2 M x 16-Bit) CMOS
中文描述： 128兆位（8米× 16位），3.0伏的CMOS只，同時(shí)作業(yè)閃存和32兆位（2米× 16位）的CMOS
文件頁(yè)數(shù)： 79/86頁(yè)
文件大小： 588K
代理商： AM49PDL127BH
December 16, 2003
Am49PDL127BH/Am49PDL129BH
77
A D V A N C E I N F O R M A T I O N
pSRAM AC CHARACTERISTICS
Write Cycle
Notes:
1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied.
2. If OE# is high during the write cycle, the outputs will remain at high impedance.
3. If CE#1ps, LB# or UB# goes low at the same time or after WE# goes low, the outputs will remain at high impedance.
4. If CE#1ps, LB# or UB# goes high at the same time or before WE# goes high, the outputs will remain at high impedance.
Figure 29.
Pseudo SRAM Write Cycle—WE# Control
Parameter
Symbol
Description
Speed
Unit
66
85
t
WC
t
WP
t
CW
t
BW
t
AW
t
AS
t
WR
t
ODW
t
OEW
t
DS
t
DH
t
CH
t
CEH
t
WEH
Write Cycle Time
Min
70
85
ns
Write Pulse Time
Min
50
60
ns
Chip Enable to End of Write
Min
60
70
ns
Data Byte Control to End of Write
Min
60
70
ns
Address Valid to End of Write
Min
60
70
ns
Address Setup Time
Min
0
ns
Write Recovery Time
Min
0
ns
WE# Low to Write to Output High-Z
Max
20
ns
WE# High to Write to Output Active
Min
0
ns
Data Set-up Time
Min
30
Data Hold from Write Time
Min
0
ns
CE2 Hold Time
Min
300
μs
Chip Enable High Pulse Width
Min
10
ns
Write Enable High Pulse Width
Min
6
ns
t
WC
t
WP
t
WR
t
CW
t
BW
Valid Data In
t
AS
t
CH
t
OEW
Addresses
A20 to A0
WE#
CE#1
CE2
LB#, UB#
D
IN
DQ15 to DQ0
D
OUT
DQ15 to DQ0
t
ODW
t
DS
t
DH
High-Z
(Note 1)
(Note 3)
(Note 4)
相關(guān)PDF資料
PDF描述
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