參數(shù)資料
型號: AM49PDL127BH
廠商: Spansion Inc.
英文描述: 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2 M x 16-Bit) CMOS
中文描述: 128兆位(8米× 16位),3.0伏的CMOS只,同時作業(yè)閃存和32兆位(2米× 16位)的CMOS
文件頁數(shù): 3/86頁
文件大?。?/td> 588K
代理商: AM49PDL127BH
ADVANCE INFORMATION
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Refer to AMD’s Website (www.amd.com) for the latest information.
Publication#
30452
Issue Date:
December 16, 2003
Rev:
A
Amendment
+3
Am49PDL127BH/Am49PDL129BH
Stacked Multi-Chip Package (MCP) Flash Memory and pSRAM
128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
and 32 Mbit (2 M x 16-Bit) CMOS Pseudo Static RAM with Page Mode
DISTINCTIVE CHARACTERISTICS
MCP Features
Power supply voltage of 2.7 to 3.3 volt
High performance
— Access time as fast as 65 ns initial / 25 ns page
Package
— 73-Ball FBGA
Operating Temperature
— –40°C to +85°C
Flash Memory Features
ARCHITECTURAL ADVANTAGES
128 Mbit Page Mode device
— Page size of 8 words: Fast page read access from random
locations within the page
Dual Chip Enable inputs (PDL129 only)
— Two CE# inputs control selection of each half of the memory
space
Single power supply operation
— Full Voltage range: 2.7 to 3.3 volt read, erase, and program
operations for battery-powered applications
Simultaneous Read/Write Operation
— Data can be continuously read from one bank while
executing erase/program functions in another bank
— Zero latency switching from write to read operations
FlexBank Architecture
— 4 separate banks, with up to two simultaneous operations
per device
— Bank A: 16 Mbit (4 Kw x 8 and 32 Kw x 31)
— Bank B: 48 Mbit (32 Kw x 96)
— Bank C: 48 Mbit (32 Kw x 96)
— Bank D: 16 Mbit (4 Kw x 8 and 32 Kw x 31)
SecSi
TM
(Secured Silicon) Sector region
— Up to 128 words accessible through a command sequence
— Up to 64 factory-locked words
— Up to 64 customer-lockable words
Both top and bottom boot blocks in one device
Manufactured on 0.13 μm process technology
20-year data retention at 125°C
Minimum 1 million erase cycle guarantee per sector
PERFORMANCE CHARACTERISTICS
High Performance
— Page access times as fast as 25 ns
— Random access times as fast as 65 ns
Power consumption (typical values at 10 MHz)
— 45 mA active read current
— 25 mA program/erase current
— 1 μA typical standby mode current
SOFTWARE FEATURES
Software command-set compatible with JEDEC 42.4
standard
— Backward compatible with Am29F and Am29LV families
CFI (Common Flash Interface) complaint
— Provides device-specific information to the system, allowing
host software to easily reconfigure for different Flash devices
Erase Suspend / Erase Resume
— Suspends an erase operation to allow read or program
operations in other sectors of same bank
Unlock Bypass Program command
— Reduces overall programming time when issuing multiple
program command sequences
相關(guān)PDF資料
PDF描述
AM49PDL127BH66IS 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2 M x 16-Bit) CMOS
AM49PDL129AH61IS 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) CMOS Pseudo Static RAM
AM49PDL127AH 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) CMOS Pseudo Static RAM
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