參數(shù)資料
型號: AM49PDL127BH85IT
廠商: SPANSION LLC
元件分類: 存儲器
英文描述: 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2 M x 16-Bit) CMOS
中文描述: SPECIALTY MEMORY CIRCUIT, PBGA73
封裝: 8 X 11.60 MM, FBGA-73
文件頁數(shù): 65/86頁
文件大?。?/td> 588K
代理商: AM49PDL127BH85IT
December 16, 2003
Am49PDL127BH/Am49PDL129BH
63
A D V A N C E I N F O R M A T I O N
FLASH AC CHARACTERISTICS
Read-Only Operations – Am29PDL127H
Notes:
1.
Not 100% tested.
2.
See Figure 11 and Table 18 for test specifications
3.
Measurements performed by placing a 50 ohm termination on the
data pin with a bias of V
/2. The time from OE# high to the data
bus driven to V
CC
/2 is taken as t
DF
.
Read-Only Operations – Am29PDL129H
Notes:
1.
Not 100% tested.
2.
See Figure 11 and Table 18 for test specifications
3.
Valid CE#f1/CE#f2 conditions: (CE#f1= V
IL
, CE#f2= V
IH
) or
(CE#f1= V
IH
, CE#f2=V
IL
).
4.
Valid CE#f1/CE#f2 transitions: (CE#f1= CE#f2= V
IH
) to (CE#f1=
V
IL
, CE#f2=V
IH
) or (CE#f1= V
IH
, CE#f2=V
IL
).
5.
Measurements performed by placing a 50 ohm termination on the
data pin with a bias of V
/2. The time from OE# high to the data
bus driven to V
CC
/2 is taken as t
DF
.
Valid CE#f1/CE#f2 transitions: (CE#f1= V
, CE#f2= V
IH
) or
(CE#f1= V
IH
, CE#f2=V
IL
) to (CE#f1= CE#f2= V
IH
).
6.
Parameter
Description
Test Setup
Speed Options
JEDEC
Std.
66
85
Unit
t
AVAV
t
RC
Read Cycle Time (Note 1)
Min
65
85
ns
t
AVQV
t
ACC
Address to Output Delay
CE#f1, OE# = V
IL
Max
65
85
ns
t
ELQV
t
CE
Chip Enable to Output Delay
OE# = V
IL
Max
65
85
ns
t
PACC
Page Access Time
Max
25
30
ns
t
GLQV
t
OE
Output Enable to Output Delay
Max
25
30
ns
t
EHQZ
t
DF
Chip Enable to Output High Z (Note 1, 3)
Max
16
ns
t
GHQZ
t
DF
Output Enable to Output High Z (Notes 1, 3)
Max
16
ns
t
AXQX
t
OH
Output Hold Time From Addresses, CE#f1 or
OE#, Whichever Occurs First (Notes 3)
Min
5
ns
t
OEH
Output Enable Hold Time
(Note 1)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
Parameter
Description
Test Setup
Speed Options
JEDEC
Std.
66
85
Unit
t
AVAV
t
RC
Read Cycle Time (Note 1)
Min
65
85
ns
t
AVQV
t
ACC
Address to Output Delay (Note 3)
CE#f1, OE# = V
IL
Max
65
85
ns
t
ELQV
t
CE
Chip Enable to Output Delay (Note 4)
OE# = V
IL
Max
65
85
ns
t
PACC
Page Access Time
Max
25
30
ns
t
GLQV
t
OE
Output Enable to Output Delay
Max
25
30
ns
t
EHQZ
t
DF
Chip Enable to Output High Z (Notes 1, 5, 6)
Max
16
ns
t
GHQZ
t
DF
Output Enable to Output High Z (Notes 1, 5)
Max
16
ns
t
AXQX
t
OH
Output Hold Time From Addresses, CE#f1/CE#f2
or OE#, Whichever Occurs First (Notes 5, 6)
Min
5
ns
t
OEH
Output Enable Hold Time
(Note 1)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
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AM49PDL129BH 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2 M x 16-Bit) CMOS
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