2-14 Revision 16 PLL Contribution鈥擯PLL
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IGLOO PLUS DC and Switching Characteristics
2-14
Revision 16
PLL Contribution鈥擯PLL
PPLL = PDC4 + PAC13 *FCLKOUT
FCLKOUT is the output clock frequency.1
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the
toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are
some examples:
The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the
clock frequency.
The average toggle rate of an 8-bit counter is 25%:
鈥� Bit 0 (LSB) = 100%
鈥� Bit 1
= 50%
鈥� Bit 2
= 25%
鈥撯€�
鈥� Bit 7 (MSB) = 0.78125%
鈥� Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled. When
nontristate output buffers are used, the enable rate should be 100%.
1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding
contribution (PAC13* FCLKOUT product) to the total PLL contribution.
Table 2-19 Toggle Rate Guidelines Recommended for Power Calculation
Component
Definition
Guideline
1
Toggle rate of VersaTile outputs
10%
2
I/O buffer toggle rate
10%
Table 2-20 Enable Rate Guidelines Recommended for Power Calculation
Component
Definition
Guideline
1
I/O output buffer enable rate
100%
2
RAM enable rate for read operations
12.5%
3
RAM enable rate for write operations
12.5%
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