Revision 16 2-23 Table 2-26 Summary of I/O Timing Characteristics鈥擲oftware Default Settings, STD Speed Gr" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� AGLP125V2-CS281
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 66/134闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA IGLOO PLUS 125K 281-CSP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 184
绯诲垪锛� IGLOO PLUS
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 3120
RAM 浣嶇附瑷�(j矛)锛� 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 212
闁€鏁�(sh霉)锛� 125000
闆绘簮闆诲锛� 1.14 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 281-TFBGA锛孋SBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 281-CSP锛�10x10锛�
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IGLOO PLUS Low Power Flash FPGAs
Revision 16
2-23
Table 2-26 Summary of I/O Timing Characteristics鈥擲oftware Default Settings, STD Speed Grade
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
I/O
S
tan
dard
Dr
ive
S
trength
Eq
uivalen
tSo
ft
ware
De
fault
Drive
S
trength
Option
1
Slew
Rat
e
Ca
p
acitive
Lo
ad
(p
F)
Ex
te
rn
al
R
esi
st
or
(
)
t DO
UT
t DP
t DI
N
t PY
)
t PYS
t EOUT
t ZL
t ZH
t LZ
t HZ
Unit
s
3.3 V LVTTL /
3.3 V LVCMOS
12 mA 12 mA High 5 pF
鈥� 0.98 2.31 0.19 0.99 1.37 0.67 2.34 1.86 2.65 3.38 ns
3.3 V LVCMOS
Wide Range2
100 A 12 mA High 5 pF
鈥� 0.98 3.21 0.19 1.32 1.92 0.67 3.21 2.52 3.73 4.73 ns
2.5 V LVCMOS
12 mA 12 mA High 5 pF
鈥� 0.98 2.29 0.19 1.19 1.40 0.67 2.32 1.94 2.65 3.27 ns
1.8 V LVCMOS
8 mA 8 mA High 5 pF
鈥� 0.98 2.45 0.19 1.12 1.61 0.67 2.48 2.16 2.71 3.16 ns
1.5 V LVCMOS
4 mA 4 mA High 5 pF
鈥� 0.98 2.71 0.19 1.26 1.80 0.67 2.75 2.39 2.78 3.15 ns
1.2 V LVCMOS
2 mA 2 mA High 5 pF
鈥� 0.98 3.380.191.572.340.673.262.782.99 3.24 ns
1.2 V LVCMOS
Wide Range3
100 A 2 mA High 5 pF 鈥� 0.98 3.38 0.19 1.57 2.34 0.67 3.26 2.78 2.99 3.24 ns
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is 卤100 A. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.
4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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AGLP125V2-CS281I 鍔熻兘鎻忚堪:IC FPGA IGLOO PLUS 125K 281-CSP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪锛� 绯诲垪:IGLOO PLUS 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛�
AGLP125-V2CS289 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
AGLP125V2-CS289 鍔熻兘鎻忚堪:IC FPGA IGLOO PLUS 125K 289-CSP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪锛� 绯诲垪:IGLOO PLUS 妯�(bi膩o)婧�(zh菙n)鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):792 RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):120 闁€鏁�(sh霉):30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:289-CSP锛�14x14锛�
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AGLP125-V2CS289I 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology