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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� AGLP125V2-CS281
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 106/134闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA IGLOO PLUS 125K 281-CSP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 184
绯诲垪锛� IGLOO PLUS
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 3120
RAM 浣嶇附瑷�(j矛)锛� 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 212
闁€鏁�(sh霉)锛� 125000
闆绘簮闆诲锛� 1.14 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 281-TFBGA锛孋SBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 281-CSP锛�10x10锛�
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IGLOO PLUS Low Power Flash FPGAs
Revision 16
2-59
1.2 V DC Core Voltage
Table 2-86 AGLP125 Global Resource
Commercial-Case Conditions: TJ = 70掳C, VCC = 1.425 V
Parameter
Description
Std.
Units
Min.1
Max.2
tRCKL
Input Low Delay for Global Clock
1.36
1.71
ns
tRCKH
Input High Delay for Global Clock
1.39
1.82
ns
tRCKMPWH
Minimum Pulse Width High for Global Clock
1.18
ns
tRCKMPWL
Minimum Pulse Width Low for Global Clock
1.15
ns
tRCKSW
Maximum Skew for Global Clock
0.43
ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-87 AGLP030 Global Resource
Commercial-Case Conditions: TJ = 70掳C, VCC = 1.14 V
Parameter
Description
Std.
Units
Min.1
Max.2
tRCKL
Input Low Delay for Global Clock
1.80
2.09
ns
tRCKH
Input High Delay for Global Clock
1.88
2.27
ns
tRCKMPWH
Minimum Pulse Width High for Global Clock
1.40
ns
tRCKMPWL
Minimum Pulse Width Low for Global Clock
1.65
ns
tRCKSW
Maximum Skew for Global Clock
0.39
ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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AGLP125V2-CS281I 鍔熻兘鎻忚堪:IC FPGA IGLOO PLUS 125K 281-CSP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪锛� 绯诲垪:IGLOO PLUS 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛�
AGLP125-V2CS289 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
AGLP125V2-CS289 鍔熻兘鎻忚堪:IC FPGA IGLOO PLUS 125K 289-CSP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪锛� 绯诲垪:IGLOO PLUS 妯�(bi膩o)婧�(zh菙n)鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):792 RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):120 闁€鏁�(sh霉):30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:289-CSP锛�14x14锛�
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AGLP125-V2CS289I 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology