2-62 Revision 13 Differential I/O Characteristics Physical Implementation Configuration of the I/O " />
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鍨嬭櫉锛� AGLE3000V2-FGG484
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 141/166闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 1KB FLASH 3M 484-FBGA
妯欐簴鍖呰锛� 60
绯诲垪锛� IGLOOe
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 75264
RAM 浣嶇附瑷堬細 516096
杓稿叆/杓稿嚭鏁�(sh霉)锛� 341
闁€鏁�(sh霉)锛� 3000000
闆绘簮闆诲锛� 1.14 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 484-BGA
渚涙噳鍟嗚ō鍌欏皝瑁濓細 484-FPBGA锛�23x23锛�
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IGLOOe DC and Switching Characteristics
2-62
Revision 13
Differential I/O Characteristics
Physical Implementation
Configuration of the I/O modules as a differential pair is handled by the Microsemi Designer software
when the user instantiates a differential I/O macro in the design.
Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output
Register (OutReg), Enable Register (EnReg), and DDR. However, there is no support for bidirectional
I/Os or tristates with the LVPECL standards.
LVDS
Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It
requires that one data bit be carried through two signal lines, so two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-23. The
building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three
board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver
resistors are different from those used in the LVPECL implementation because the output standard
specifications are different.
Along with LVDS I/O, IGLOOe also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)
configuration (up to 40 nodes).
Figure 2-23 LVDS Circuit Diagram and Board-Level Implementation
140
100
Z0 = 50
165
165
+
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P
N
P
N
INBUF_LVDS
OUTBUF_LVDS
FPGA
Bourns Part Number: CAT16-LV4F12
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