2-32 Revision 13 Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AGLE3000V2-FGG484
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 108/166闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 1KB FLASH 3M 484-FBGA
妯欐簴鍖呰锛� 60
绯诲垪锛� IGLOOe
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 75264
RAM 浣嶇附瑷堬細 516096
杓稿叆/杓稿嚭鏁�(sh霉)锛� 341
闁€鏁�(sh霉)锛� 3000000
闆绘簮闆诲锛� 1.14 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 484-BGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 484-FPBGA锛�23x23锛�
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�鐣跺墠绗�108闋�绗�109闋�绗�110闋�绗�111闋�绗�112闋�绗�113闋�绗�114闋�绗�115闋�绗�116闋�绗�117闋�绗�118闋�绗�119闋�绗�120闋�绗�121闋�绗�122闋�绗�123闋�绗�124闋�绗�125闋�绗�126闋�绗�127闋�绗�128闋�绗�129闋�绗�130闋�绗�131闋�绗�132闋�绗�133闋�绗�134闋�绗�135闋�绗�136闋�绗�137闋�绗�138闋�绗�139闋�绗�140闋�绗�141闋�绗�142闋�绗�143闋�绗�144闋�绗�145闋�绗�146闋�绗�147闋�绗�148闋�绗�149闋�绗�150闋�绗�151闋�绗�152闋�绗�153闋�绗�154闋�绗�155闋�绗�156闋�绗�157闋�绗�158闋�绗�159闋�绗�160闋�绗�161闋�绗�162闋�绗�163闋�绗�164闋�绗�165闋�绗�166闋�
IGLOOe DC and Switching Characteristics
2-32
Revision 13
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor鈥揟ransistor Logic is a general purpose standard (EIA/JESD) for 3.3 V
applications. It uses an LVTTL input buffer and push-pull output buffer. The 3.3 V LVCMOS standard is
supported as part of the 3.3 V LVTTL support.
Table 2-34 Minimum and Maximum DC Input and Output Levels
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH IOL IOH
IOSH
IOSL
IIL1 IIH2
Drive Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmA mA
Max.
mA3
Max.
mA3
A4 A4
4 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
4
25
27
10 10
8 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
8
51
54
10 10
12 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
12 12
103
109
10 10
16 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
16 16
132
127
10 10
24 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
24 24
268
181
10 10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where 鈥�0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100掳C junction temperature) and maximum voltage.
4. Currents are measured at 85掳C junction temperature.
5. Software default selection highlighted in gray.
Figure 2-7 AC Loading
Table 2-35 AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (typ.) (V)
CLOAD (pF)
03.3
1.4
鈥�
5
Note: *Measuring point = Vtrip. See Table 2-23 on page 2-23 for a complete table of trip points.
Test Point
Enable Path
Datapath
35 pF
R = 1 k
R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
5 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
M1A3PE3000L-FG484I IC FPGA 1KB FLASH 3M 484-FBGA
A3PE3000L-FG484I IC FPGA 1KB FLASH 3M 484-FBGA
M1AGLE3000V2-FG484 IC FPGA 1KB FLASH 3M 484-FBGA
EP4CGX150DF31I7N IC CYCLONE IV FPGA 150K 896FBGA
AMM22DTBT-S189 CONN EDGECARD 44POS R/A .156 SLD
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
AGLE3000V2-FGG484I 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 3M 484-FBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:IGLOOe 妯欐簴鍖呰:1 绯诲垪:ProASICPLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:129024 杓稿叆/杓稿嚭鏁�(sh霉):248 闁€鏁�(sh霉):600000 闆绘簮闆诲:2.3 V ~ 2.7 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:- 灏佽/澶栨:352-BFCQFP锛屽付鎷夋】 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:352-CQFP锛�75x75锛�
AGLE3000V2-FGG896 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 3M 896-FBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:IGLOOe 妯欐簴鍖呰:1 绯诲垪:ProASICPLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:129024 杓稿叆/杓稿嚭鏁�(sh霉):248 闁€鏁�(sh霉):600000 闆绘簮闆诲:2.3 V ~ 2.7 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:- 灏佽/澶栨:352-BFCQFP锛屽付鎷夋】 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:352-CQFP锛�75x75锛�
AGLE3000V2-FGG896ES 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE3000V2-FGG896I 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 3M 896-FBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:IGLOOe 妯欐簴鍖呰:1 绯诲垪:ProASICPLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:129024 杓稿叆/杓稿嚭鏁�(sh霉):248 闁€鏁�(sh霉):600000 闆绘簮闆诲:2.3 V ~ 2.7 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:- 灏佽/澶栨:352-BFCQFP锛屽付鎷夋】 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:352-CQFP锛�75x75锛�
AGLE3000V2-FGG896PP 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology