參數(shù)資料
型號： ADV7393
廠商： Analog Devices, Inc.
英文描述： Low Power, Chip Scale 10-Bit SD/HD Video Encoder
中文描述： 低功耗，芯片尺寸10位標清/高清視頻編碼器
文件頁數(shù)： 91/96頁
文件大?。?/td> 1209K
代理商： ADV7393
ADV7390/ADV7391/ADV7392/ADV7393
Table 96. 16-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress
Setting Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x10
ED-SDR input mode.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x1C
625p @ 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
Rev. 0 | Page 91 of 96
Table 97. 16-Bit 625p YCrCb In, RGB Out
Subaddress
Setting Description
0x17
0x02
0x00
0x1C
0x01
0x10
0x02
0x10
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
625p @ 50 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
0x30
0x18
0x31
0x01
Table 98. 8-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30
0x04
525p @ 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
Table 99. 10-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30
0x04
525p @ 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
0x33
0x6C
10-bit input enabled.
Table 100. 8-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x04
525p @ 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
Table 101. 10-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x04
525p @ 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
0x33
0x6C
10-bit input enabled.
Table 102. 8-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30
0x1C
625p @ 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
Table 103. 10-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30
0x1C
625p @ 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
0x33
0x6C
10-bit input enabled.
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ADV7393BCPZ Low Power, Chip Scale 10-Bit SD/HD Video Encoder
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相關代理商/技術參數(shù)
參數(shù)描述
ADV7393BCPZ 功能描述:IC DAC VIDEO HDTV 10BIT 40LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799
ADV7393BCPZ-REEL 功能描述:IC DAC ENCODER VID HDTV 40-LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799
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ADV7393EBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder
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