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參數(shù)資料
| 型號(hào)： | ADV7393 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| 中文描述： | 低功耗，芯片尺寸10位標(biāo)清/高清視頻編碼器 |
| 文件頁數(shù)： | 37/96頁 |
| 文件大?。?/td> | 1209K |
| 代理商： | ADV7393 |
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ADV7390/ADV7391/ADV7392/ADV7393
Table 26. Register 0x8A to Register 0x98
SR7 to
SR0
Register
0x8A
SD Timing Register 0
Rev. 0 | Page 37 of 96
Bit Description
SD Slave/Master Mode.
Bit Number
4
0
1
0
1
Register Setting
Slave mode
Master mode
Mode 0
Mode 1
Mode 2
Mode 3
No delay
2 clock cycles
4 clock cycles
6 clock cycles
40 IRE
7.5 IRE
A low-high-low transition
resets the internal SD
timing counters
t
a
= 1 clock cycle
t
a
= 4 clock cycles
t
a
= 16 clock cycles
t
a
= 128 clock cycles
t
b
= 0 clock cycles
t
b
= 4 clock cycles
t
b
= 8 clock cycles
t
b
= 18 clock cycles
t
c
= t
b
t
c
= t
b
+ 32 μs
1 clock cycle
4 clock cycles
16 clock cycles
128 clock cycles
0 clock cycles
1 clock cycle
2 clock cycles
3 clock cycles
Subcarrier Frequency
Bits[7:0]
Subcarrier Frequency
Bits[15:8]
Subcarrier Frequency
Bits[23:16]
Subcarrier Frequency
Bits[31:24]
Subcarrier Phase Bits[9:2]
Extended Data Bits[7:0]
Extended Data Bits[15:8].
Data Bits[7:0]
Data Bits[15:8]
Setting any of these bits
to 1 disables pedestal
on the line number
indicated by the bit
settings
Reset
Value
0x08
7
x
6
0
1
5
0
0
1
1
3
1
2
0
0
1
1
1
0
1
0
1
0
0
1
SD Timing Mode.
Reserved.
SD Luma Delay.
SD Minimum Luma Value.
SD Timing Reset.
0
0
1
1
x
0
1
0
1
x
x
x
0
0
1
1
x
0
1
0
1
0
1
x
0
0
1
1
x
0
1
0
1
x
0
0
1
1
x
0
1
0
1
x
0x00
SD HSYNC Width.
SD HSYNC to VSYNC Delay.
SD HSYNC to VSYNC Rising
Edge Delay (Mode 1 Only).
VSYNC Width (Mode 2 Only).
0x8B
SD Timing Register 1
Note: Applicable in
master modes only,
that is, Subaddress
0x8A, Bit 0 = 1.
HSYNC to Pixel Data Adjust.
0x8C
SD F
SC
Register 0
1
Subcarrier Frequency Bits[7:0]
0x1F
0x8D
SD F
SC
Register 1
1
Subcarrier Frequency Bits[15:8]
x
x
x
x
x
x
x
x
0x7C
0x8E
SD F
SC
Register 2
1
Subcarrier Frequency Bits[23:16]
x
x
x
x
x
x
x
x
0xF0
0x8F
SD F
SC
Register 3
1
Subcarrier Frequency Bits[31:24]
x
x
x
x
x
x
x
x
0x21
0x90
0x91
0x92
0x93
0x94
0x95
0x96
0x97
0x98
1
SD subcarrier frequency registers default to NTSC subcarrier frequency values.
SD F
SC
Phase
SD Closed Captioning
SD Closed Captioning
SD Closed Captioning
SD Closed Captioning Data on Odd Fields.
SD Pedestal Register 0
SD Pedestal Register 1
SD Pedestal Register 2
SD Pedestal Register 3
Subcarrier Phase Bits[9:2]
Extended Data on Even Fields.
Extended Data on Even Fields.
Data on Odd Fields.
x
x
x
x
x
17
25
17
25
x
x
x
x
x
16
24
16
24
x
x
x
x
x
15
23
15
23
x
x
x
x
x
14
22
14
22
x
x
x
x
x
13
21
13
21
x
x
x
x
x
12
20
12
20
x
x
x
x
x
11
19
11
19
x
x
x
x
x
10
18
10
18
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Pedestal on Odd Fields.
Pedestal on Odd Fields.
Pedestal on Even Fields.
Pedestal on Even Fields.
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