參數(shù)資料
型號(hào): ADV7310
廠商: Analog Devices, Inc.
英文描述: Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs
中文描述: 多格式視頻編碼器216兆赫六噪聲整形的12位DAC
文件頁(yè)數(shù): 34/84頁(yè)
文件大?。?/td> 1099K
代理商: ADV7310
REV. A
–34–
ADV7310/ADV7311
TIMING MODES
HD Async Timing Mode
[Subaddress 10h, Bit 3, 2]
For any input data that does not conform to the standards select-
able in input mode, Subaddress 10h, asynchronous timing mode
can be used to interface to the ADV7310/ADV7311. Timing control
signals for
HSYNC
,
VSYNC
, and
BLANK
have to be programmed
by the user. Macrovision and programmable oversampling rates
are not available in async timing mode.
CLK
ACTIVE VIDEO
PROGRAMMABLE
INPUT TIMING
ANALOG
OUTPUT
81
66
66
243
1920
HORIZONTAL SYNC
e
d
c
b
a
P_HSYNC
P_VSYNC
P_BLANK
SET ADDRESS 10h,
BIT 6 TO 1
Figure 29a. Async Timing Mode—Programming Input Control Signals for SMPTE 295M Compatibility
ACTIVE VIDEO
0
1
HORIZONTAL SYNC
e
d
c
b
a
CLK
P_HSYNC
P_VSYNC
P_BLANK
SET ADDRESS 10h,
BIT 6 TO 1
ANALOG OUTPUT
Figure 29b. Async Timing Mode—Programming Input Control Signals for Bilevel Sync Signal
In async mode, the PLL must be turned off [Subaddress 00h,
Bit 1 = 1].
Figures 29a and 29b show examples of how to program the
ADV7310/ADV7311 to accept a different high definition standard
other than SMPTE 293M, SMPTE 274M, SMPTE 296M, or
ITU-R BT.1358.
The following truth table must be followed when programming the
control signals in async timing mode. For standards that do not
require a tri-sync level,
P_BLANK
must be tied low at all times.
相關(guān)PDF資料
PDF描述
ADV7310KST Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs
ADV7311 Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs
ADV7311KST Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs
ADV7312 Multiformat 11-Bit HDTV Video Encoder
ADV7312KST Multiformat 11-Bit HDTV Video Encoder
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