參數(shù)資料
型號(hào)： ADV7202KSTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/28頁(yè)
文件大小： 0K
描述： IC CODEC VIDEO 10BIT 64LQFP
產(chǎn)品變化通告： ADV7xxx Obsolescence 16/Jan/2012
標(biāo)準(zhǔn)包裝： 1
類型： 視頻編解碼器
數(shù)據(jù)接口： 串行
分辨率（位）： 12，10 b
ADC / DAC 數(shù)量： 1 / 4
三角積分調(diào)變： 無(wú)
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
電壓 - 電源，數(shù)字： 4.75 V ~ 5.25 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤
REV. 0
ADV7202
–17–
MODE REGISTER 2
MR2 (MR20–MR27)
(Address (SR4–SR0) = 02H)
Figure 18 shows the various operations under the control of
Mode Register 2.
MR2 BIT DESCRIPTION
Analog Input Configuration (MR20–MR23)
This control selects the analog input configuration, up to five
CVBS input channels, or two component YUV, or three S-Video
and eight auxiliary inputs. See Figure 18 for details.
SHA0 Control (MR24)
Setting this bit to “0” enables SHA0; otherwise, this SHA is
powered down (SHA = Sample and Hold Amplifier).
SHA1 Control (MR25)
Setting this bit to “0” enables SHA1; otherwise, this SHA is
powered down.
SHA2 Control (MR26)
Setting this bit to “0” enables SHA2; otherwise, this SHA is
powered down.
AUX Control (MR27)
Setting this bit to “0” enables the auxiliary ADC; otherwise,
Aux ADC is powered down.
ANALOG INPUT CONFIGURATION
MR23 MR22 MR21 MR20
0
CVBS IN ON AIN1
0
1
CVBS IN ON AIN2
00
10
CVBS IN ON AIN3
0
1
RESERVED
01
00
CVBS IN ON AIN5
01
CVBS IN ON AIN6
01
10
Y/C IN ON AIN1, AIN4
0
1
Y/C IN ON AIN2, AIN3
1
0
YUV IN ON AIN2, AIN3, AIN6
1
0
1
CVBS IN ON AIN1, 8 AUX INPUTS
10
CVBS IN ON AIN2, 8 AUX INPUTS
MR21
MR27
MR22
MR24
MR26
MR23
MR20
MR25
MR26
0
NORMAL
1POWER-DOWN
SHA2 CONTROL
MR27
0
NORMAL
1POWER-DOWN
AUX CONTROL
MR25
0
NORMAL
1POWER-DOWN
SHA1 CONTROL
MR24
0
NORMAL
1POWER-DOWN
SHA0 CONTROL
Figure 18. Mode Register 2
MODE REGISTER 3
MR3 (MR30–MR37)
(Address (SR4–SR0) = 03H)
Figure 19 shows the various operations under the control of
Mode Register 3.
MR3 BIT DESCRIPTION
Clamp Current (MR30)
Setting this bit to “1” enables the halving of all clamp currents.
Analog Input Mode (MR31)
Setting this bit to “1” enables differential mode for the analog
inputs; otherwise, the inputs are single-ended. See Figure 19.
SHA Gain (MR32)
Setting this bit to “0” enables SHA gain of 1. If the bit is set to “1,”
the SHA gain is 2. The SHA gain will limit the input signal range.
See Figure 19.
Voltage Clamp (MR33)
Setting this bit to “1” will enable the voltage clamps.
Output Enable (MR34)
Setting this bit to “1” puts the digital outputs into high
impedance.
SYNC Polarity (MR35)
This bit controls the polarity of the SYNC_IN pin. If the bit is set
to “0,” a logic low pulse corresponds to H-Sync. If the bit is “1,”
a logic high pulse corresponds to H-Sync. This sync in pulse can
then be used to control the synchronization of AGC/Clamping.
See AR12.
Reserved (MR36–MR37)
Zero must be written to both these registers.
MR37
MR32
MR34
MR36
MR34
0
NORMAL
1
HIGH Z
OUTPUT ENABLE
MR35
0LOW
1
HIGH
SYNC POLARITY
MR33
MR31
MR30
MR33
0OFF
1ON
VOLTAGE CLAMP
MR32
01
12
SHA GAIN
MR30
0
NORMAL
1
HALF
CLAMP CURRENT
MR31
0SINGLE-ENDED
1
DIFFERENTIAL
ANALOG INPUT
MR37–MR36
ZERO MUST BE
WRITTEN TO
THESE REGISTERS
Figure 19. Mode Register 3
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