參數(shù)資料
型號(hào): ADV7202KSTZ
廠商: Analog Devices Inc
文件頁數(shù): 14/28頁
文件大?。?/td> 0K
描述: IC CODEC VIDEO 10BIT 64LQFP
產(chǎn)品變化通告: ADV7xxx Obsolescence 16/Jan/2012
標(biāo)準(zhǔn)包裝: 1
類型: 視頻編解碼器
數(shù)據(jù)接口: 串行
分辨率(位): 12,10 b
ADC / DAC 數(shù)量: 1 / 4
三角積分調(diào)變:
電壓 - 電源,模擬: 4.75 V ~ 5.25 V
電壓 - 電源,數(shù)字: 4.75 V ~ 5.25 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
REV. 0
ADV7202
–21–
TIMING REGISTER
TR (TR00–TR07)
(Address (SR4–SR0) = 0AH)
Figure 25 shows the various operations under the control of the
Timing Register.
TR BIT DESCRIPTION
Crystal Oscillator Circuit (TR00)
If this bit is set to “0,” the internal oscillator circuit will be
disabled. Disabling the oscillator circuit is possible when an
external clock module is used, thus saving power.
ADC Bias Currents (TR01)
If this bit is set to “1,” all analog bias currents will be doubled.
Duty Cycle Equalizer (TR03)
When this bit is set to “1,” the clock duty cycle equalizer circuit
is active. This will only have an effect on the ADC operation.
The digital core clock will not be affected.
Clock Delay (TR05–TR06)
Using these two bits, it is possible to insert a delay in the clock
signal to the digital core. These bits control the insertion of
the delay.
Reserved (TR02, TR04, TR07)
Zero must be written to the bits in these registers.
TR01
TR02
TR04
TR05
TR06
ZERO MUST BE
WRITTEN TO
THIS BIT
TR07
TR03
TR00
0
DISABLE
1ENABLE
CRYSTAL
OSCILLATOR CIRCUIT
TR06
TR05
00
0ns
01
4ns
10
6ns
11
8ns
CLOCK DELAY
TR03
0
INACTIVE
1ACTIVE
DUTY CYCLE
EQUALIZER
TR01
0
NORMAL
1
DOUBLE
ADC BIAS
CURRENTS
ZERO MUST BE
WRITTEN TO
THIS BIT
ZERO MUST BE
WRITTEN TO
THIS BIT
TR04
TR02
TR07
Figure 25. Timing Register 0
VREF ADJUST REGISTER
VR (VR00–VR07)
(Address (SR4–SR0) = 0BH)
Figure 26 shows the various operations under the control of the
VREF Adjust Register.
VR BIT DESCRIPTION
Reserved (VR00)
This register is reserved and “1” must be written to this bit.
Reserved (VR01–VR03)
Zero must be written to these registers.
ADC Reference Voltage Adjust (VR04–VR06)
By setting the value of this 3-bit word, it is possible to trim the
ADC internal voltage reference VREFADC.
Reserved (VR07)
Zero must be written to this register.
VR01
VR07
VR02
VR04
VR05
VR06
ZERO MUST BE
WRITTEN TO
THIS BIT
VR07
VR03
VR00
VR06 VR05
VR04
00
0DEFAULT NOMINAL
00
1
+14mV
01
0
+28mV
01
1
+42mV
10
0
–14mV
10
1
–28mV
11
0
–42mV
11
1
–56mV
ADC REFERENCE VOLTAGE ADJUST
ZERO MUST BE
WRITTEN TO
THESE BITS
VR03–VR01
ONE MUST BE
WRITTEN TO
THIS BIT
VR00
Figure 26. ADC VREF Register
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