參數(shù)資料
型號: ADV7181BST
廠商: ANALOG DEVICES INC
元件分類: 顏色信號轉換
英文描述: Multiformat SDTV Video Decoder
中文描述: COLOR SIGNAL DECODER, PQFP64
封裝: LEAD FREE, MS-026BCD, LQFP-64
文件頁數(shù): 7/96頁
文件大?。?/td> 873K
代理商: ADV7181BST
ADV7181B
TIMING SPECIFICATIONS
Guaranteed by characterization. At A
VDD
= 3.15 V to 3.45 V, D
VDD
= 1.65 V to 2.0 V, D
VDDIO
= 3.0 V to 3.6 V, P
VDD
= 1.65 V to 2.0 V
(operating temperature range, unless otherwise noted).
Table 3.
Parameter
Symbol
Test Conditions
SYSTEM CLOCK AND CRYSTAL
Nominal Frequency
Frequency Stability
I
2
C PORT
SCLK Frequency
SCLK Min Pulse Width High
t
1
SCLK Min Pulse Width Low
t
2
Hold Time (Start Condition)
t
3
Setup Time (Start Condition)
t
4
SDA Setup Time
t
5
SCLK and SDA Rise Time
t
6
SCLK and SDA Fall Time
t
7
Setup Time for Stop Condition
t
8
RESET FEATURE
Reset Pulse Width
CLOCK OUTPUTS
LLC1 Mark Space Ratio
t
9
:t
10
DATA AND CONTROL OUTPUTS
Data Output Transitional Time
t
11
Negative Clock Edge to start of valid
data. (t
ACCESS
= t
10
– t
11
)
Data Output Transitional Time
t
12
End of valid data to negative clock
edge. (t
HOLD
= t
9
+ t
12
)
Rev. 0 | Page 7 of 96
Min
0.6
1.3
0.6
0.6
100
5
45:55
Typ
27.00
0.6
Max
±50
400
300
300
55:45
3.4
Unit
MHz
ppm
kHz
μs
μs
μs
μs
ns
ns
ns
μs
ms
% Duty Cycle
ns
2.4
ns
ANALOG SPECIFICATIONS
Guaranteed by characterization. At A
VDD
= 3.15 V to 3.45 V, D
VDD
= 1.65 V to 2.0 V, D
VDDIO
= 3.0 V to 3.6 V, P
VDD
= 1.65 V to 2.0 V
(operating temperature range, unless otherwise noted).
Table 4.
Parameter
Symbol
Test Conditions
CLAMP CIRCUITRY
External Clamp Capacitor
Input Impedance
Clamps switched off
Large Clamp Source Current
Large Clamp Sink Current
Fine Clamp Source Current
Fine Clamp Sink Current
Min
Typ
0.1
10
0.75
0.75
60
60
Max
Unit
μF
M
mA
mA
μA
μA
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