參數(shù)資料
型號: ADV7181
廠商: Analog Devices, Inc.
英文描述: Multiformat SDTV Video Decoder
中文描述: 標(biāo)清多格式視頻解碼器
文件頁數(shù): 79/96頁
文件大小: 873K
代理商: ADV7181
ADV7181B
Rev. 0 | Page 79 of 96
Bits
4
Subaddress
0x34
Register
HS
Position
Control 1
Bit Description
HSE[10:8]. HS end allows the
positioning of the HS output within
the video line.
Reserved
HSB[10:8]. HS begin allows the
positioning of the HS output within
the video line.
Reserved
HSB[7:0] See above, using HSB[10:0]
and HSE[10:0], the user can program
the position and length of HS output
signal.
HSE[7:0] See above.
7
6
5
3
2
0
1
0
0
0
Comments
HS output ends HSE[10:0]
pixels after the falling edge
of HSync
Set to 0
HS output starts HSB[10:0]
pixels after the falling edge
of HSync
Set to 0
Notes
Using HSB and HSE
the user can
program the
position and length
of the output HSync
0
0
0
0
0
0
0
0
0
0
0
1
0
0x35
HS
Position
Control 2
0x36
HS
Position
Control 3
Polarity
0
0
0
0
0
0
0
0
0
1
Invert polarity
Normal polarity as per the
timing diagrams
Set to 0
Active high
Active low
Set to 0
Active high
Active low
Set to 0
Active high
Active low
PCLK. Sets the polarity of LLC1.
Reserved
PF. Sets the FIELD polarity.
0
1
0
0
1
0
0
1
0
0
Reserved
PVS. Sets the VS Polarity.
Reserved
PHS. Sets HS Polarity.
0x37
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