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參數(shù)資料
| 型號： | ADV7181 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat SDTV Video Decoder |
| 中文描述： | 標清多格式視頻解碼器 |
| 文件頁數(shù)： | 10/96頁 |
| 文件大?。?/td> | 873K |
| 代理商： | ADV7181 |
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ADV7181B
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 10 of 96
1
HS
2
DGND
DVDDIO
3
4
P11
P10
P9
P8
SFL
5
6
7
8
9
DGND
10
DVDDIO
11
NC
12
NC
13
P7
14
P6
15
P5
16
AIN5
AIN4
AIN3
AGND
CAPC2
AGND
CML
REFOUT
AVDD
CAPY2
CAPY1
AGND
AIN2
AIN1
DGND
NC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P
17
P
18
P
19
L
20
X
21
X
22
D
23
D
24
P
25
P
26
N
27
N
28
P
29
E
30
P
31
A
32
V
64
F
63
P
62
P
61
P
60
P
59
D
58
D
57
N
56
N
55
S
54
S
53
A
52
R
51
N
50
A
49
ADV7181B
TOP VIEW
(Not to Scale)
NC = NO CONNECT
0
PIN 1
INTRQ
Figure 4. 64-Lead LFCSP/LQFP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
3, 10, 24, 34, 57
32, 37, 43, 45
4, 11
23, 58
40
31
35, 36, 46–49
12, 13, 27, 28, 33,
50, 55, 56
26, 25, 19, 18, 17,
16, 15, 14, 8, 7, 6, 5,
62, 61, 60, 59
2
64
63
1
Mnemonic
DGND
AGND
DVDDIO
DVDD
AVDD
PVDD
AIN1–AIN6
NC
Type
G
G
P
P
P
P
I
Function
Digital Ground.
Analog Ground.
Digital I/O Supply Voltage (3.3 V).
Digital Core Supply Voltage (1.8 V).
Analog Supply Voltage (3.3 V).
PLL Supply Voltage (1.8 V).
Analog Video Input Channels.
No Connect Pins.
P0–P15
O
Video Pixel Output Port.
HS
VS
FIELD
INTRQ
O
O
O
O
Horizontal Synchronization Output Signal.
Vertical Synchronization Output Signal.
Field Synchronization Output Signal.
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input
video. See the interrupt register map in Table 82.
I
2
C Port Serial Data Input/Output Pin.
I
2
C Port Serial Clock Input (Maximum Clock Rate of 400 kHz).
This pin selects the I
2
C address for the ADV7181B. ALSB set to a Logic 0 sets the address for
a write as 0x40; for ALSB set to a logic high, the address selected is 0x42.
System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to
reset the ADV7181B circuitry.
This is a line-locked output clock for the pixel data output by the ADV7181B. Nominally
27 MHz, but varies up or down according to video line length.
This is the input pin for the 27 MHz crystal, or can be overdriven by an external 3.3 V,
27 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
53
54
52
SDA
SCLK
ALSB
I/O
I
I
51
RESET
I
20
LLC
O
22
XTAL
I
相關PDF資料 |
PDF描述 |
|---|---|
| ADV7181B | Multiformat SDTV Video Decoder |
| ADV7181BBCPZ | Multiformat SDTV Video Decoder |
| ADV7181BBSTZ | Multiformat SDTV Video Decoder |
| ADV7181BCP | Multiformat SDTV Video Decoder |
| ADV7181BST | Multiformat SDTV Video Decoder |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7181B | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder |
| ADV7181BBCPZ | 制造商:Analog Devices 功能描述:Video Decoder 3ADC 9-Bit 64-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:ADV718XB DECODER FAMILY UPDATES - Bulk 制造商:Analog Devices 功能描述:IC VIDEO ENCODER |
| ADV7181BBSTZ | 制造商:Analog Devices 功能描述:Video Decoder 3ADC 9-Bit 64-Pin LQFP 制造商:Analog Devices 功能描述:IC VIDEO ENCODER |
| ADV7181BCP | 制造商:Analog Devices 功能描述:Video Decoder 3ADC 9-Bit 64-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:10BIT NTSC/PAL/SECAM VIDEO DECODER I.C. - Bulk |
| ADV7181BCPZ | 制造商:Analog Devices 功能描述: |
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