The ADV7180 supports a 2-wire (I2
參數(shù)資料
型號： ADV7180BST48Z
廠商： Analog Devices Inc
文件頁數(shù)： 93/116頁
文件大?。?/td> 0K
描述： IC VID DECOD SDTV 10BIT 48LQFP
標(biāo)準(zhǔn)包裝： 1
類型： 視頻解碼器
應(yīng)用： 數(shù)碼相機(jī)，手機(jī)，便攜式視頻
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤
ADV7180
Data Sheet
Rev. I | Page 78 of 116
MPU PORT DESCRIPTION
The ADV7180 supports a 2-wire (I2C-compatible) serial interface.
Two inputs, serial data (SDATA) and serial clock (SCLK), carry
information between the ADV7180 and the system I2C master
controller. Each slave device is recognized by a unique address.
The ADV7180 I2C port allows the user to set up and configure
the decoder and to read back the captured VBI data. The ADV7180
has four possible slave addresses for both read and write operations,
depending on the logic level of the ALSB pin. The four unique
addresses are shown in Table 104. The ADV7180 ALSB pin
controls Bit 1 of the slave address. By altering the ALSB, it is
possible to control two ADV7180s in an application without the
conflict of using the same slave address. The LSB (Bit 0) sets
either a read or write operation. Logic 1 corresponds to a read
operation, and Logic 0 corresponds to a write operation.
Table 104. I2C Address for ADV7180
ALSB
R/W
Slave Address
0
0x40
0
1
0x41
1
0
0x42
1
0x43
To control the device on the bus, a specific protocol must be
followed. First, the master initiates a data transfer by establishing a
start condition, which is defined by a high-to-low transition on
SDATA while SCLK remains high. This indicates that an address/
data stream follows. All peripherals respond to the start condition
and shift the next eight bits (the 7-bit address plus the R/W bit).
The bits are transferred from MSB down to LSB. The peripheral
that recognizes the transmitted address responds by pulling the
data line low during the ninth clock pulse; this is known as an
acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition is
where the device monitors the SDATA and SCLK lines for the
start condition and the correct transmitted address. The R/W
bit determines the direction of the data. Logic 0 on the LSB of
the first byte means that the master writes information to the
peripheral. Logic 1 on the LSB of the first byte means that the
master reads information from the peripheral.
The ADV7180 acts as a standard slave device on the bus. The
data on the SDATA pin is eight bits long, supporting the 7-bit
address plus the R/W bit. The device has 249 subaddresses to
enable access to the internal registers. Therefore, it interprets
the first byte as the device address and the second byte as the
starting subaddress. The subaddresses auto-increment, allowing
data to be written to or read from the starting subaddress. A data
transfer is always terminated by a stop condition. The user can
also access any unique subaddress register on a one-by-one
basis without updating all the registers.
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, they cause an immediate jump
to the idle condition. During a given SCLK high period, the user
should only issue one start condition, one stop condition, or a
single stop condition followed by a single start condition. If an
invalid subaddress is issued by the user, the ADV7180 does not
issue an acknowledge and returns to the idle condition.
In auto-increment mode, if the user exceeds the highest
subaddress, the following action is taken:
In read mode, the highest subaddress register contents
continue to be output until the master device issues a no
acknowledge. This indicates the end of a read. A no
acknowledge condition occurs when the SDATA line is
not pulled low on the ninth pulse.
In write mode, the data for the invalid byte is not loaded
into any subaddress register. A no acknowledge is issued by
the ADV7180, and the part returns to the idle condition.
SDATA
SCLK
START ADDR
ACK
DATA
ACK
STOP
SUBADDRESS
1–7
8
9
8
9
1–7
8
9
S
P
R/W
05
70
0-
04
4
Figure 53. Bus Data Transfer
S
WRITE
SEQUENCE
SLAVE ADDR
A(S)
SUB ADDR
A(S)
DATA
A(S)
DATA
A(S)
P
S
READ
SEQUENCE
SLAVE ADDR
A(S)
SUB ADDR
A(S) S
A(S)
DATA
A(M)
DATA
A(M) P
S = START BIT
P= STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A(S) = NO ACKNOWLEDGE BY SLAVE
A(M) = NO ACKNOWLEDGE BY MASTER
LSB = 1
LSB = 0
057
00
-04
5
Figure 54. Read and Write Sequence
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