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參數(shù)資料
| 型號： | ADV7180BCPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | 10-Bit, 4 x Oversampling SDTV Video Decoder |
| 中文描述： | COLOR SIGNAL DECODER, QCC40 |
| 封裝： | 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, LFCSP-40 |
| 文件頁數(shù)： | 19/112頁 |
| 文件大?。?/td> | 1320K |
| 代理商： | ADV7180BCPZ |
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ADV7180
GLOBAL CONTROL REGISTERS
Register control bits listed in this section affect the whole chip.
POWER-SAVING MODES
Power-Down
PDBP, Address 0x0F [2]
The digital supply of the ADV7180 can be shut down by using
the (PWRDWN) pin or via I
2
C (PWRDWN, see below). PDBP
controls whether the I
2
C control or the pin has the higher
priority. The default is to give the pin (PWRDWN) priority.
This allows the user to have the ADV7180 powered down by
default at power-up without the need for an I
2
C write.
When PDBD is 0 (default), the digital supply power is controlled
by the PWRDWN pin (the PWRDWN bit is disregarded).
Rev. A | Page 19 of 112
When PDBD is 1, the PWRDWN bit, 0x0F[5], has priority
(the pin is disregarded).
PWRDWN, Address 0x0F [5]
When PDBP is set to 1, setting the PWRDWN bit switches the
ADV7180 to a chip-wide power-down mode. The power-down
stops the clock from entering the digital section of the chip,
thereby freezing its operation. No I
2
C bits are lost during
power-down. The PWRDWN bit also affects the analog blocks
and switches them into low current modes. The I
2
C interface is
unaffected and remains operational in power-down mode.
The ADV7180 leaves the power-down state if the PWRDWN bit is
set to 0 (via I
2
C) or if the ADV7180 is reset using the RESET pin.
PDBP must be set to 1 for the PWRDWN bit to power down
the ADV7180.
When PWRDWN is 0 (default), the chip is operational.
When PWRDWN is 1, the ADV7180 is in a chip-wide
power-down mode.
RESET CONTROL
RESET, Chip Reset, Address 0x0F [7]
Setting this bit, which is equivalent to controlling the RESET
pin on the ADV7180, issues a full chip reset. All I
2
C registers
are reset to their default/power-up values. Note that some
register bits do not have a reset value specified. They keep their
last written value. Those bits are marked as having a reset value
of x in the register tables (Table 103 and Table 104). After the
reset sequence, the part immediately starts to acquire the
incoming video signal.
After setting the RESET bit (or initiating a reset via the RESET pin),
the part returns to the default for its primary mode of operation.
All I
2
C bits are loaded with their default values, making this bit
self-clearing.
Executing a software reset takes approximately 2 ms. However,
it is recommended to wait 5 ms before any further I
2
C writes are
performed.
The I
2
C master controller receives a no acknowledge condition
on the ninth clock cycle when chip reset is implemented. See
the MPU Port Description section.
When RESET is 0 (default), operation is normal.
When RESET is 1, the reset sequence starts.
GLOBAL PIN CONTROL
Three-State Output Drivers
TOD, Address 0x03 [6]
This bit allows the user to three-state the output drivers of the
ADV7180.
Upon setting the TOD bit, the P15 to P0 (P7 to P0 for the
ADV7180 LFCSP-40), HS, VS, FIELD (VS/FIELD pin for the
ADV7180 LFCSP-40), and SFL pins are three-stated.
The timing pins (HS, VS, FIELD) can be forced active via the
TIM_OE bit. For more information on three-state control, refer
to the Three-State LLC Driver and the Timing Signals Output
Enable sections.
Individual drive strength controls are provided via the
DR_STR_XX bits.
When TOD is 0 (default), the output drivers are enabled.
When TOD is 1, the output drivers are three-stated.
Three-State LLC Driver
TRI_LLC, Address 0x1D [7]
This bit allows the output drivers for the LLC pin of the
ADV7180 to be three-stated. For more information on three-
state control, refer to the Three-State Output Drivers and the
Timing Signals Output Enable sections.
Individual drive strength controls are provided via the
DR_STR_XX bits.
When TRI_LLC is 0 (default), the LLC pin drivers work
according to the DR_STR_C[1:0] setting (pin enabled).
When TRI_LLC is 1, the LLC pin drivers are three-stated.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADV7180BSTZ | 10-Bit, 4 x Oversampling SDTV Video Decoder |
| ADV7181 | Multiformat SDTV Video Decoder |
| ADV7181B | Multiformat SDTV Video Decoder |
| ADV7181BBCPZ | Multiformat SDTV Video Decoder |
| ADV7181BBSTZ | Multiformat SDTV Video Decoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7180BCPZ | 制造商:Analog Devices 功能描述:IC VIDEO DECODER 10BIT 57.27MSPS LFCSP40 |
| ADV7180BCPZ-REEL | 功能描述:IC VIDEO DECODER SDTV 40-LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應(yīng)用:移動電話，手機(jī)，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| ADV7180BST48Z | 功能描述:IC VID DECOD SDTV 10BIT 48LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:電平移位器 應(yīng)用:LCD 電視機(jī)/監(jiān)控器 安裝類型:表面貼裝 封裝/外殼:28-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:28-WQFN（4x4）裸露焊盤 包裝:帶卷 (TR) 其它名稱:296-32523-2TPS65198RUYT-ND |
| ADV7180BST48Z-RL | 功能描述:視頻 IC 48-Lead Low Profile Quad Flat Package RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| ADV7180BSTZ | 功能描述:IC VIDEO DECODER SDTV 64-LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:電平移位器 應(yīng)用:LCD 電視機(jī)/監(jiān)控器 安裝類型:表面貼裝 封裝/外殼:28-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:28-WQFN（4x4）裸露焊盤 包裝:帶卷 (TR) 其它名稱:296-32523-2TPS65198RUYT-ND |
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