參數(shù)資料
型號: ADV7180BCPZ
廠商: ANALOG DEVICES INC
元件分類: 顏色信號轉(zhuǎn)換
英文描述: 10-Bit, 4 x Oversampling SDTV Video Decoder
中文描述: COLOR SIGNAL DECODER, QCC40
封裝: 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, LFCSP-40
文件頁數(shù): 13/112頁
文件大?。?/td> 1320K
代理商: ADV7180BCPZ
ADV7180
64-LEAD LQFP
Rev. A | Page 13 of 113
64
V
63
F
62
P
61
P
60
P
59
P
58
D
57
D
56
G
55
G
54
S
53
S
52
A
51
R
50
N
49
A
I
6
47
A
IN
4
46
A
IN
3
45
NC
42
NC
43
AGND
44
NC
48
A
IN
5
41
NC
40
AVDD
39
VREFN
37
AGND
36
A
IN
2
35
A
IN
1
34
TEST_0
33
NC
38
VREFP
2
HS
3
DGND
4
DVDDIO
7
P9
P8
6
P10
5
P11
1
INTRQ
8
9
SFL
10
DGND
12
GPO1
13
GPO0
14
P7
15
P6
16
P5
11
DVDDIO
17
P
18
P
19
P
20
L
21
X
22
X
23
D
24
D
25
P
26
P
27
N
28
N
29
P
30
E
31
P
32
A
PIN 1
ADV7180
LQFP
TOP VIEW
(Not to Scale)
NC = NO CONNECT
0
Figure 8. 64-Lead LQFP Pin Configuration
Table 9. Pin Function Description for the ADV7180 LQFP-64
Pin No.
Mnemonic
3, 10, 24, 57
DGND
32, 37, 43
AGND
4, 11
DVDDIO
23, 58
DVDD
40
AVDD
31
PVDD
38
VREFP
39
VREFN
35, 36, 46 to 49
A
IN
1 to A
IN
6
27, 28, 33, 41, 42,
44, 45, 50
5 to 8, 14 to 19,
25, 26, 59 to 62
P7 to P2, P1,
P0, P15 to P12
2
HS
64
VS
63
FIELD
1
INTRQ
Type
G
G
P
P
P
P
O
O
I
Function
Digital Ground.
Analog Ground.
Digital I/O Supply Voltage (3.3 V).
Digital Supply Voltage (1.8 V).
Analog Supply Voltage (1.8 V).
PLL Supply Voltage (1.8 V).
Internal Voltage Reference Output. See Figure 54 for recommended output circuitry.
Internal Voltage Reference Output. See Figure 54 for recommended output circuitry.
Analog Video Input Channels.
No Connect Pins. These pins are not connected internally.
NC
P11 to P8,
O
Video Pixel Output Port. See Table 96 for output configuration for 8-bit and 16-bit modes.
O
O
O
O
Horizontal Synchronization Output Signal.
Vertical Synchronization Output Signal.
Field Synchronization Output Signal.
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input
video (see Table 104).
I
2
C Port Serial Data Input/Output Pin.
I
2
C Port Serial Clock Input. Maximum clock rate of 400 kHz.
This pin selects the I
2
C address for the ADV7180. For ALSB set to Logic 0, the address
selected for a write is 0x40; for ALSB set to logic high, the address selected is 0x42.
A logic low on this pin places the ADV7180 in power-down mode.
The recommended external loop filter must be connected to the ELPF pin, as shown in
Figure 54.
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset
the ADV7180 circuitry.
53
54
52
SDATA
SCLK
ALSB
I/O
I
I
29
30
PWRDWN
ELPF
I
I
51
RESET
I
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