參數(shù)資料
型號(hào): ADV7179BCP
廠商: ANALOG DEVICES INC
元件分類: 顏色信號(hào)轉(zhuǎn)換
英文描述: Chip Scale PAL/NTSC Video Encoder with Advanced Power Management
中文描述: COLOR SIGNAL ENCODER, QCC40
封裝: 6 X 6 MM, MO-220VJJD-2, LFCSP-40
文件頁數(shù): 33/52頁
文件大?。?/td> 488K
代理商: ADV7179BCP
ADV7174/ADV7179
TIMING MODE REGISTER 0 (TR0)
Bits:
TR07–TR00
Address:
SR4–SR0 = 07H
Rev. A | Page 33 of 52
Figure 43 shows the various operations under the control of Timing Register 0. This register can be read from as well as written to.
TR01
TR00
TR07
TR02
TR03
TR05
TR06
TR04
TIMING
REGISTER RESET
TR07
BLANK INPUT
CONTROL
TR03
0
1
ENABLE
DISABLE
PIXEL PORT
CONTROL
TR06
0
1
8 BIT
FORBIDDEN
MASTER/SLAVE
CONTROL
TR00
0
1
SLAVE TIMING
MASTER TIMING
LUMA DELAY
0
0
1
1
0ns DELAY
74ns DELAY
148ns DELAY
222ns DELAY
0
1
0
1
TR05 TR04
TIMING MODE
SELECTION
TR02 TR01
0
0
1
1
MODE 0
MODE 1
MODE 2
MODE 3
0
1
0
1
0
Figure 43. Timing Register 0
Table 15. TR0 Bit Description
Bit Name
Master/Slave Control
Timing Mode Selection
Bit No.
TR00
TR02–TR01
Description
This bit controls whether the ADV7174/ADV7179 is in master or slave mode.
These bits control the timing mode of the ADV7174/ADV7179. These modes are
described in more detail in the 3.3 V Timing Specifications table.
This bit controls whether the BLANK input is used when the part is in slave mode.
These bits control the addition of a luminance delay. Each bit represents a delay of
74 ns.
This bit is used to set the pixel port to accept 8-bit or YCrCb data on Pins P7–P0.
0 must be written here.
Toggling the TR07 from low to high and to low again resets the internal timing
counters. This bit should be toggled after power-up, reset, or changing to a new
timing mode.
BLANK Input Control
Luma Delay
TR03
TR05–TR04
Pixel Port Control
TR06
Timing Register Reset
TR07
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