參數(shù)資料
型號(hào): ADV7176A
廠商: Analog Devices, Inc.
英文描述: High Quality, 10-Bit, Digital CCIR-601 to PAL/NTSC Video Encoder
中文描述: 高品質(zhì),10位,數(shù)字無線電咨詢委員會(huì),601到PAL / NTSC制式視頻編碼器
文件頁數(shù): 28/52頁
文件大小: 629K
代理商: ADV7176A
ADV7175A/ADV7176A
–28–
REV. B
APPE NDIX 1
BOARD DE SIGN AND LAY OUT CONSIDE RAT IONS
T he ADV7175A/ADV7176A is a highly integrated circuit contain-
ing both precision analog and high speed digital circuitry. It has
been designed to minimize interference effects on the integrity
of the analog circuitry by the high speed digital circuitry. It is
imperative that these same design and layout techniques be
applied to the system level design so that high speed, accurate
performance is achieved. T he “Recommended Analog Circuit
Layout” shows the analog interface between the device and
monitor.
The layout should be optimized for lowest noise on the ADV7175A/
ADV7176A power and ground lines by shielding the digital
inputs and providing good decoupling. T he lead length between
groups of V
AA
and GND pins should by minimized to minimize
inductive ringing.
Ground Planes
T he ground plane should encompass all ADV7175A/ADV7176A
ground pins, voltage reference circuitry, power supply bypass
circuitry for the ADV7175A/ADV7176A, the analog output traces,
and all the digital signal traces leading up to the ADV7175A/
ADV7176A. T he ground plane is the board’s common ground
plane.
T his should be as substantial as possible to maximize heat
spreading and power dissipation on the board.
Power Planes
T he ADV7175A/ADV7176A and any associated analog circuitry
should have its own power plane, referred to as the analog
power plane (V
AA
). T his power plane should be connected to
the regular PCB power plane (V
CC
) at a single point through a
ferrite bead. T his bead should be located within three inches of
the ADV7175A/ADV7176A.
T he metallization gap separating device power plane and board
power plane should be as narrow as possible to minimize the
obstruction to the flow of heat from the device into the general
board.
T he PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV7175A/ADV7176A power pins and voltage
reference circuitry.
Plane-to-plane noise coupling can be reduced by ensuring that
portions of the regular PCB power and ground planes do not
overlay portions of the analog power plane unless they can be
arranged so that the plane-to-plane noise is common-mode.
Supply Decoupling
For optimum performance, bypass capacitors should be in-
stalled using the shortest leads possible, consistent with reliable
operation, to reduce the lead inductance. Best performance is
obtained with 0.1
μ
F ceramic capacitor decoupling. Each
group of V
AA
pins on the ADV7175A/ADV7176A must have at
least one 0.1
μ
F decoupling capacitor to GND. T hese capaci-
tors should be placed as close to the device as possible.
It is important to note that while the ADV7175A/ADV7176A
contains circuitry to reject power supply noise, this rejection
decreases with frequency. If a high frequency switching power
supply is used, the designer should pay close attention to reduc-
ing power supply noise and consider using a three terminal voltage
regulator for supplying power to the analog power plane.
Digital Signal Interconnect
T he digital inputs to the ADV7175A/ADV7176A should be
isolated as much as possible from the analog outputs and other
analog circuitry. Also, these input signals should not overlay
the analog power plane.
Due to the high clock rates involved, long clock lines to the
ADV7175A/ADV7176A should be avoided to reduce noise
pickup.
Any active termination resistors for the digital inputs should be
connected to the regular PCB power plane (V
CC
) and not the
analog power plane.
Analog Signal Interconnect
T he ADV7175A/ADV7176A should be located as close to the
output connectors as possible to minimize noise pickup and
reflections due to impedance mismatch.
T he video output signals should overlay the ground plane, not
the analog power plane, to maximize the high frequency power
supply rejection.
Digital inputs, especially pixel data inputs and clocking signals,
should never overlay any of the analog signal circuitry and
should be kept as far away as possible.
For best performance, the outputs should each have a 75
load resistor connected to GND. T hese resistors should be
placed as close as possible to the ADV7175A/ADV7176A as to
minimize reflections.
T he ADV7175A/ADV7176A should have no inputs left float-
ing. Any inputs that are not required should be tied to ground.
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