參數(shù)資料
型號(hào): ADV7176A
廠商: Analog Devices, Inc.
英文描述: High Quality, 10-Bit, Digital CCIR-601 to PAL/NTSC Video Encoder
中文描述: 高品質(zhì),10位,數(shù)字無(wú)線電咨詢委員會(huì),601到PAL / NTSC制式視頻編碼器
文件頁(yè)數(shù): 27/52頁(yè)
文件大?。?/td> 629K
代理商: ADV7176A
ADV7175A/ADV7176A
–27–
REV. B
T able I. DAC Output Configuration Matrix
MR06
MR26
MR37
DAC A
DAC B
DAC C
DAC D
Simultaneous Output
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CVBS
Y
CVBS
Y
CVBS
G
CVBS
Y
CVBS
CVBS
CVBS
CVBS
B
B
U
U
C
C
C
C
R
R
V
V
Y
CVBS
Y
CVBS
G
CVBS
Y
CVBS
2 Composite and Y/C
2 Composite and Y/C
2 Composite and Y/C
2 Composite and Y/C
RGB and Composite
RGB and Composite
YUV and Composite
YUV and Composite
T E LE T E X T CONT ROL RE GIST E R T C07 (T C07–T C00)
(Address [SR4–SR0] = 24H)
T eletext Control Register is an 8-bit wide register.
T T X RE Q Rising E dge Control (T C07–T C04)
T hese bits control the position of the rising edge of T T X REQ.
It can be programmed from zero CLOCK cycles to a max of 15
CLOCK cycles—see Figure 48.
T T X RE Q Falling E dge Control (T C03–T C00)
T hese bits control the position of the falling edge of T T X REQ.
It can be programmed from zero CLOCK cycles to a max of 15
CLOCK cycles. T his controls the active window for teletext
data. Increasing this value reduces the amount of teletext bits
below the default of 360. If bits T C03–T C00 are unchanged
when bits T C07–T C04 are changed, the falling edge of T T REQ
will track that of the rising edge (i.e., the time between the fall-
ing and rising edge remains constant)—see Figure 48.
Figure 43. Teletext Control Register
TC01
TC00
TC07
TC02
TC04
TC03
TC05
TC06
TTXR EQ RISING EDGE CONTROL
TC07 TC06
TC05 TC04
0
0
"
1
1
0
0
"
1
1
0
0
"
1
1
0
1
"
0
1
0 PCLK
1 PCLK
" PCLK
14 PCLK
15 PCLK
TTXR EQ FALLING EDGE CONTROL
TC03 TC02
TC01 TC00
0
0
"
1
1
0
0
"
1
1
0
0
"
1
1
0
1
"
0
1
0 PCLK
1 PCLK
" PCLK
14 PCLK
15 PCLK
Input Default Color (MR36)
T his bit determines the default output color from the DACs for
zero input data (or disconnected). A Logical “0” means that the
color corresponding to 00000000 will be displayed. A Logical
“1” forces the output color to black for 00000000 input video
data.
DAC Switching Control (MR37)
T his bit is used to switch the DAC outputs from SCART to a
EUROSCART configuration. A complete table of all DAC
output configurations is shown below.
CVBS: Composite Video Baseband Signal
Y:
Luminance Component Signal (For YUV or Y/C Mode)
C:
Chrominance Signal (For Y/C Mode)
U:
Chrominance Component Signal (For YUV Mode)
V:
Chrominance Component Signal (For YUV Mode)
R:
RED Component Video (For RGB Mode)
G:
GREEN Component Video (For RGB Mode)
B:
BLUE Component Video (For RGB Mode)
MR31
MR30
MR37
MR32
MR34
MR33
MR35
MR36
MR30
REV CODE
(READ ONLY)
INPUT DEFAULT COLOR
MR36
0
1
INPUT COLOR
BLACK
VBI PASSTHROUGH
MR31
0
1
DISABLE
ENABLE
RESERVED
TELETEXT ENABLE
MR34
0
1
DISABLE
ENABLE
MR35 = 0
ZERO SHOULD
BE WRITTEN TO
THIS BIT
DAC OUTPUT
SWITCHING
0
1
COMPOSITE
GREEN/LUMA/Y
MR37
DAC A
BLUE/COMP/U
BLUE/COMP/U
DAC B
RED/CHROMA/V
RED/CHROMA/V
DAC C
GREEN/LUMA/Y
COMPOSITE
DAC D
Figure 42. Mode Register 3
NOT E
Each DAC can be individually powered ON or OFF with the following control bits
(“0” = ON, “1” = OFF):
MR13 - DAC C
MR14 - DAC D
MR15 - DAC B
MR16 - DAC A
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