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ADV7175/ADV7176
REV. A
–22–
APPE NDIX 1
BOARD DE SIGN AND LAY OUT CONSIDE RAT IONS
operation, to reduce the lead inductance. Best performance is
obtained with 0.1
μ
F ceramic capacitor decoupling. Each group
of V
AA
pins on the ADV7175/ADV7176 must have at least one
0.1
μ
F decoupling capacitor to GND. T hese capacitors should
be placed as close as possible to the device.
It is important to note that while the ADV7175/ADV7176
contains circuitry to reject power supply noise, this rejection
decreases with frequency. If a high frequency switching power
supply is used, the designer should pay close attention to reduc-
ing power supply noise and consider using a three terminal volt-
age regulator for supplying power to the analog power plane.
Digital Signal Interconnect
T he digital inputs to the ADV7175/ADV7176 should be iso-
lated as much as possible from the analog outputs and other
analog circuitry. Also, these input signals should not overlay
the analog power plane.
Due to the high clock rates involved, long clock lines to the
ADV7175/ADV7176 should be avoided to reduce noise pickup.
Any active termination resistors for the digital inputs should be
connected to the regular PCB power plane (V
CC
), and not the
analog power plane.
Analog Signal Interconnect
T he ADV7175/ADV7176 should be located as close as possible
to the output connectors to minimize noise pickup and reflec-
tions due to impedance mismatch.
T he video output signals should overlay the ground plane, and
not the analog power plane, to maximize the high frequency
power supply rejection.
Digital inputs, especially pixel data inputs and clocking signals
should never overlay any of the analog signal circuitry and
should be kept as far away as possible.
For best performance, the outputs should each have a 75
load resistor connected to GND. T hese resistors should be
placed as close as possible to the ADV7175/ADV7176 so as to
minimize reflections.
T he ADV7175/ADV7176 should have no inputs left floating.
Any inputs that are not required should be tied to ground.
T he ADV7175/ADV7176 is a highly integrated circuit contain-
ing both precision analog and high speed digital circuitry. It has
been designed to minimize interference effects on the integrity
of the analog circuitry by the high speed digital circuitry. It is
imperative that these same design and layout techniques be ap-
plied to the system level design such that high speed, accurate
performance is achieved. T he “Recommended Analog Circuit
Layout” shows the analog interface between the device and
monitor.
T he layout should be optimized for lowest noise on the
ADV7175/ADV7176 power and ground lines by shielding the
digital inputs and providing good decoupling. T he lead length
between groups of V
AA
and GND pins should by minimized so
as to minimize inductive ringing.
Ground Planes
T he ground plane should encompass all ADV7175/ADV7176
ground pins, voltage reference circuitry, power supply bypass
circuitry for the ADV7175/ADV7176, the analog output traces,
and all the digital signal traces leading up to the ADV7175/
ADV7176. T he ground plane is the board’s common ground
plane.
Power Planes
T he ADV7175/ADV7176 and any associated analog circuitry
should have its own power plane, referred to as the analog
power plane (V
AA
). T his power plane should be connected to
the regular PCB power plane (V
CC
) at a single point through a
ferrite bead. T his bead should be located within three inches of
the ADV7175/ADV7176.
T he PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV7175/ADV7176 power pins and voltage refer-
ence circuitry.
Plane-to-plane noise coupling can be reduced by ensuring that
portions of the regular PCB power and ground planes do not
overlay portions of the analog power plane, unless they can be
arranged such that the plane-to-plane noise is common mode.
Supply Decoupling
For optimum performance, bypass capacitors should be in-
stalled using the shortest leads possible, consistent with reliable