參數(shù)資料
型號(hào)： ADV7176
廠商： Analog Devices, Inc.
英文描述： Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder
中文描述： 綜合數(shù)字無(wú)線電咨詢委員會(huì)，601 YCrCb到PAL / NTSC制式視頻編碼器
文件頁(yè)數(shù)： 16/36頁(yè)
文件大?。?/td> 447K
代理商： ADV7176
ADV7175/ADV7176
REV. A
–16–
MPU PORT DE SCRIPT ION
T he ADV7175 and ADV7176 support a two wire serial (I
2
C
compatible) microprocessor bus driving multiple peripherals.
T wo inputs serial data (SDAT A) and serial clock (SCLOCK )
carry information between any device connected to the bus.
Each slave device is recognized by a unique address. T he
ADV7175 and ADV7176 each have four possible slave ad-
dresses for both read and write operations. T hese are unique
addresses for each device and are illustrated in Figure 26 and
Figure 27. T he LSB sets either a read or write operation.
Logic Level “1” corresponds to a read operation while Logic
Level “0” corresponds to a write operation. A1 is set by setting
the ALSB pin of the ADV7175/ADV7176 to Logic Level “0” or
Logic Level “1.”
1
X
1
0
1
0
1
A1
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
0
1
WRITE
READ
Fig 26. ADV7175 Slave Address
0
X
1
0
1
0
1
A1
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
0
1
WRITE
READ
Fig 27. ADV7176 Slave Address
T o control the various devices on the bus the following protocol
must be followed. First the master initiates a data transfer by es-
tablishing a start condition, defined by a high to low transition
on SDAT A while SCLOCK remains high. T his indicates that
an address/data stream will follow. All peripherals respond to
the start condition and shift the next eight bits (7-bit address +
R/
W
bit). T he bits transferred from MSB down to LSB. T he
peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse. T his is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. T he idle
condition is where the device monitors the SDAT A and SCLOCK
lines waiting for the Start condition and the correct transmitted
address. T he R/
W
bit determines the direction of the data. A
Logic “0” on the LSB of the first byte means that the master
will write information to the peripheral. A Logic “1” on the
LSB of the first byte means that the master will read informa-
tion from the peripheral.
T he ADV7175/ADV7176 acts as a standard slave device on the
bus. T he data on the SDAT A pin is 8 bits long supporting the
7-bit addresses plus the R/
W
bit. T he ADV7175 has 33 sub-
addresses and the ADV7176 has 19 subaddresses to enable ac-
cess to the internal registers. It, therefore, interprets the first
byte as the device address and the second byte as the starting
subaddress. T he subaddresses auto increment allowing data to
be written to or from the starting subaddress. A data transfer is
always terminated by a stop condition. T he user can also access
any unique subaddress register on a one by one basis without
having to update all the registers. T here is one exception. T he
Subcarrier Frequency Registers should be updated in sequence,
starting with Subcarrier Frequency Register 0. T he auto incre-
ment function should be then used to increment and access
subcarrier frequency registers 1, 2 and 3. T he subcarrier fre-
quency registers should not be accessed independently.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of se-
quence with normal read and write operations, then these cause
an immediate jump to the idle condition. During a given
SCLOCK high period the user should only issue one start con-
dition, one stop condition or a single stop condition followed by
a single start condition. If an invalid subaddress is issued by the
user, the ADV7175/ADV7176 will not issue an acknowledge
and will return to the idle condition. If in auto-increment
mode, the user exceeds the highest subaddress then the follow-
ing action will be taken:
1. In Read Mode the highest subaddress register contents will
continue to be output until the master device issues a no-ac-
knowledge. T his indicates the end of a read. A no-acknowledge
condition is where the SDAT A line is not pulled low on the
ninth pulse.
2. In Write Mode, the data for the invalid byte will be not be
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7175/ADV7176 and the part will re-
turn to the idle condition.
Figure 28 illustrates an example of data transfer for a read se-
quence and the start and stop conditions.
1-7
8
9
1-7
8
9
1-7
8
9
P
S
START ADDR R/
W
ACK SUBADDRESS ACK
DATA
ACK
STOP
SDATA
SCLOCK
Figure 28. Bus Data Transfer
Figure 29 shows bus write and read sequences.
DATA
A(S)
S
SLAVE ADDR
A(S)
SUB ADDR
A(S)
LSB = 0
LSB = 1
DATA
A(S)
P
S
SLAVE ADDR
A(S)
SUB ADDR
A(S) S
SLAVE ADDR
A(S)
DATA
A(M)
A
(M)
DATA
P
WRITE
SEQUENCE
READ
SEQUENCE
A
(S) = NO-ACKNOWLEDGE BY SLAVE
A
(M) = NO-ACKNOWLEDGE BY MASTER
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
S = START BIT
P = STOP BIT
Figure 29. Write and Read Sequences
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PDF描述
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