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ADV7172/ADV7173
–36–
REV. A
SUBCARRIER FREQUENCY REGISTERS 3–0
(FSC3–FSC0)
(Address (SR4–SR0) = 0CH–0FH)
These 8-bit-wide registers are used to set up the subcarrier
frequency. The value of these registers is calculated by using the
following equation:
Subcarrier Frequency
Re
gister
f
f
CLK
SCF
=2
32
–1
×
Example: NTSC Mode,
f
CLK
= 27 MHz,
f
SCF
= 3.5795454 MHz
Subcarrier FrequencyValue
=2
32
–
.
1
27 10
3 579454 10
6
6
×
= 21
F
07
C
16
HEX
Figure 54 shows how the frequency is set up by the four
registers.
SUBCARRIER PHASE REGISTER (FP7–FP0)
(Address (SR4–SR0) = 10H)
This 8-bit-wide register is used to set up the subcarrier phase.
Each bit represents 1.41
°
. For normal operation this register is
set to 00Hex.
SUBCARRIER
FREQUENCY
REG 3
SUBCARRIER
FREQUENCY
REG 2
SUBCARRIER
FREQUENCY
REG 1
SUBCARRIER
FREQUENCY
REG 0
FSC30
FSC29
FSC27
FSC25
FSC28
FSC24
FSC31
FSC26
FSC22
FSC21
FSC19
FSC17
FSC20
FSC16
FSC23
FSC18
FSC14
FSC13
FSC11
FSC9
FSC12
FSC8
FSC15
FSC10
FSC6
FSC5
FSC3
FSC1
FSC4
FSC0
FSC7
FSC2
Figure 54. Subcarrier Frequency Registers
CLOSED CAPTIONING EVEN FIELD
DATA REGISTER 1–0 (CED15–CED00)
(Address (SR4–SR0) = 11–12H)
These 8-bit wide registers are used to set up the closed captioning
extended data bytes on even fields. Figure 55 shows how the
high and low bytes are set up in the registers.
BYTE 1
BYTE 0
CED6
CED5
CED3
CED1
CED4
CED0
CED7
CED2
CED14 CED13
CED11
CED9
CED12
CED8
CED15
CED10
Figure 55. Closed Captioning Extended Data Register
CLOSED CAPTIONING ODD FIELD
DATA REGISTER 1–0 (CCD15–CCD00)
(Subaddress (SR4–SR0) = 13–14H)
These 8-bit-wide registers are used to set up the closed captioning
data bytes on odd fields. Figure 56 shows how the high and low
bytes are set up in the registers.
BYTE 1
CCD14
CCD13
CCD11
CCD9
CCD12
CCD8
CCD15
CCD10
BYTE 0
CCD6
CCD5
CCD3
CCD1
CCD4
CCD0
CCD7
CCD2
Figure 56. Closed Captioning Data Register
NTSC PEDESTAL/PAL TELETEXT CONTROL
REGISTERS 3–0 (PCE15–0, PCO15–0)/(TXE15–0, TXO15–0)
(Subaddress (SR4–SR0) = 15–18H)
These 8-bit-wide registers are used to enable the NTSC pedes-
tal/PAL Teletext on a line-by-line basis in the vertical blanking
interval for both odd and even fields. Figures 57 and 58 show
the four control registers. A Logic “1” in any of the bits of
these registers has the effect of turning the Pedestal OFF on
the equivalent line when used in NTSC. A Logic “1” in any of
the bits of these registers has the effect of turning Teletext ON
on the equivalent line when used in PAL.
FIELD 1/3
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
PCO6
PCO5
PCO3
PCO1
PCO4
PCO0
PCO7
PCO2
FIELD 1/3
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
PCO14
PCO13
PCO11
PCO9
PCO12
PCO8
PCO15
PCO10
FIELD 2/4
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
PCE6
PCE5
PCE3
PCE1
PCE4
PCE0
PCE7
PCE2
FIELD 2/4
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
PCE14
PCE13
PCE11
PCE9
PCE12
PCE8
PCE15
PCE10
Figure 57. Pedestal Control Registers
FIELD 2/4
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
TXE14
TXE13
TXE11
TXE9
TXE12
TXE8
TXE15
TXE10
FIELD 1/3
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9
LINE 8
LINE 7
TXO6
TXO5
TXO3
TXO1
TXO4
TXO0
TXO7
TXO2
FIELD 1/3
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
TXO14
TXO13
TXO11
TXO9
TXO12
TXO8
TXO15
TXO10
FIELD 2/4
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9
LINE 8
LINE 7
TXE6
TXE5
TXE3
TXE1
TXE4
TXE0
TXE7
TXE2
Figure 58. Teletext Control Registers