參數(shù)資料
型號: ADV7173
廠商: Analog Devices, Inc.
英文描述: Digital PAL/NTSC Video Encoder with Six DACs 10 Bits, Color Control and Enhanced Power Management
中文描述: 數(shù)碼PAL / NTSC視頻編碼器與六DAC的10位,色彩控制和增強的電源管理
文件頁數(shù): 27/59頁
文件大?。?/td> 455K
代理商: ADV7173
ADV7172/ADV7173
–27–
REV. A
MODE REGISTER 0 MR0 (MR07–MR00)
(Address (SR4–SR0) = 00H)
Figure 44 shows the various operations under the control of
Mode Register 0.
MR0 BIT DESCRIPTION
Encode Mode Control (MR01–MR00)
These bits are used to set up the encoder mode. The ADV7172/
ADV7173 can be set up to output NTSC, PAL (B, D, G, H, I),
PAL M or PAL N standard video.
Luminance Filter Control (MR02–MR04)
These bits specify which luma filter is to be selected. The filter
selection is made independent of whether PAL or NTSC is
selected.
Chrominance Filter Control (MR05–MR07)
These bits select the chrominance filter. A low-pass filter can be
selected with a choice of cutoff frequencies, (0.65 MHz, 1.0 MHz,
1.3 MHz or 2 MHz) along with a choice of CIF or QCIF filters.
CHROMA FILTER SELECT
MR07 MR06
0 0 0 1.3 MHz LOW-PASS FILTER
0 0 1 0.65 MHz LOW-PASS FILTER
0 1 0 1.0 MHz LOW-PASS FILTER
0 1 1 2.0 MHz LOW-PASS FILTER
1 0 0 RESERVED
1 0 1 CIF
1 1 0 QCIF
1 1 1 RESERVED
MR05
MR01
MR00
MR07
MR02
MR03
MR05
MR06
MR04
OUTPUT VIDEO
STANDARD SELECTION
MR01 MR00
0 0 NTSC
0 1 PAL (B, D, G, H, I)
1 0 PAL (M)
1 1 PAL (N)
LUMA FILTER SELECT
MR02
MR04 MR03
0 0 0 LOW-PASS FILTER (NTSC)
0 0 1 LOW-PASS FILTER (PAL)
0 1 0 NOTCH FILTER (NTSC)
0 0 1 NOTCH FILTER (PAL)
1 0 0 EXTENDED MODE
1 0 1 CIF
1 1 0 QCIF
1 1 1 RESERVED
Figure 44. Mode Register 0 (MR0)
MR11
MR10
MR17
MR12
MR13
MR15
MR16
MR14
LOW POWER MODE
CONTROL
MR16
0
1
DISABLE
ENABLE
MR14
0
1
DAC A
DAC C CONTROL
MR15
0
POWER-DOWN
1
NORMAL
MR17
(0)
ZERO SHOULD BE
WRITTEN TO
THIS BIT
POWER-DOWN
NORMAL
DAC B
DAC C CONTROL
DAC C
DAC C CONTROL
MR13
0
POWER-DOWN
1
NORMAL
DAC E
DAC C CONTROL
MR11
0
1
POWER-DOWN
NORMAL
MR12
0
1
POWER-DOWN
NORMAL
DAC D
DAC C CONTROL
DAC F
DAC C CONTROL
MR10
0
POWER-DOWN
1
NORMAL
Figure 45. Mode Register 1 (MR1)
MODE REGISTER 1 MR1 (MR17–MR10)
(Address (SR4–SR0) = 01H)
Figure 45 shows the various operations under the control of
Mode Register 1.
MR1 BIT DESCRIPTION
DAC Control (MR15–MR10)
MR15–MR10 bits can be used to power down the DACs. This
can be used to reduce the power consumption of the ADV7172/
ADV7173 if any of the DACs are not required in the application.
Low Power Control (MR16)
This bit enables the lower power mode of the ADV7172/
ADV7173. This will reduce by approximately 50% the average
supply current consumed by each large DAC which is powered
on. For each DAC in low power mode, the relationship between
R
SET1
/V
REF
and the output current is unchanged by this (see
Appendix 8). This bit is only relevant to the larger DACs,
DACs A, B and C. DACs D, E and F are not affected by this low
power mode.
Reserved (MR17)
A Logic “0” must be written to this bit.
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PDF描述
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