參數(shù)資料
型號: ADV7171
廠商: Analog Devices, Inc.
英文描述: Digital PAL/NTSC Video Encoder(數(shù)字PAL/NTSC視頻編碼器)
中文描述: 數(shù)碼PAL / NTSC視頻編碼器(數(shù)字PAL / NTSC制式視頻編碼器)
文件頁數(shù): 19/55頁
文件大小: 580K
代理商: ADV7171
ADV7170/ADV7171
–19–
REV. 0
622
623
624
625
1
2
3
4
5
6
7
21
22
23
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
HSYNC
BLANK
VSYNC
DISPLAY
309
310
311
312
313
314
315
316
317
318
319
334
335
336
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
HSYNC
BLANK
DISPLAY
320
VSYNC
Figure 28. Timing Mode 2 (PAL)
Mode 2: Master Option
HSYNC
,
VSYNC
,
BLANK
(Timing Register 0 TR0 = X X X X X 1 0 1)
In this mode the ADV7170/ADV7171 can generate horizontal and vertical SYNC signals. A coincident low transition of both
HSYNC
and
VSYNC
inputs indicates the start of an Odd Field. A
VSYNC
low transition when
HSYNC
is high indicates the start
of an even field. The
BLANK
signal is optional. When the
BLANK
input is disabled, the ADV7170/ADV7171 automatically blanks
all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 27 (NTSC) and Figure 28 (PAL). Figure 29 illus-
trates the
HSYNC
,
BLANK
and
VSYNC
for an even-to-odd field transition relative to the pixel data. Figure 30 illustrates the
HSYNC
,
BLANK
and
VSYNC
for an odd-to-even field transition relative to the pixel data.
PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2
HSYNC
VSYNC
BLANK
PIXEL
DATA
PAL = 132 * CLOCK/2
NTSC = 122 * CLOCK/2
Cb
Y
Cr
Y
Figure 29. Timing Mode 2 Even-to-Odd Field Transition Master/Slave
PAL = 864 * CLOCK/2
NTSC = 858 * CLOCK/2
PAL = 132 * CLOCK/2
NTSC = 122 * CLOCK/2
HSYNC
VSYNC
BLANK
PIXEL
DATA
PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2
Cb
Y
Cr
Y
Cb
Figure 30. Timing Mode 2 Odd-to-Even Field Transition Master/Slave
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