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ADV7128
REV. 0
–4–
ABSOLUT E MAX IMUM RAT INGS
*
V
AA
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7 V
Voltage on Any Digital Pin . . . . . . GND –0.5 V to V
AA
+0.5 V
Ambient Operating T emperature (T
A
) . . . . . . . . 0
°
C to +70
°
C
Storage T emperature (T
S
) . . . . . . . . . . . . . . .–65
°
C to +150
°
C
Junction T emperature (T
J
) . . . . . . . . . . . . . . . . . . . . . +150
°
C
Lead T emperature (Soldering, 10 secs) . . . . . . . . . . . . +300
°
C
Vapor Phase Soldering (2 minutes) . . . . . . . . . . . . . . . +220
°
C
I
OUT
to GND
1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to V
AA
NOT ES
*
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
1
Analog Output Short Circuit to any Power Supply or Common can be of an
indefinite duration.
PIN CONFIGURAT ION
1
2
3
7
28
27
26
22
8
9
10
21
20
19
11
12
18
17
4
5
25
24
6
23
TOP VIEW
(Not to Scale)
13
14
16
15
ADV7128
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
R
SET
COMP
GND
GND
CLOCK
V
AA
I
OUT
V
AA
V
AA
V
AA
V
AA
V
AA
V
AA
V
AA
V
AA
V
AA
V
AA
V
REF
WARNING!
ESD SENSITIVE DEVICE
C AUT ION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV7128 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN FUNCT ION DE SCRIPT ION
Pin
Mnemonic
Function
CLOCK
Clock input (T T L compatible). T he rising edge of CLOCK latches the R0–R9, G0–G9, B0–B9,
SYNC
and
BLANK
pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be driven
by a dedicated T T L buffer.
Data inputs (T T L compatible). Data is latched on the rising edge of CLOCK . D0 is the least significant data bit.
Unused data inputs should be connected to either the regular PCB power or ground plane.
Current output. T his high impedance current source is capable of directly driving a doubly terminated 75
coaxial cable.
Full-scale adjust control. A resistor (R
SET
) connected between this pin and GND, controls the magnitude of the
full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current.
T he relationship between R
SET
and the full-scale output current on I
OUT
is given by:
I
OUT
(mA) = 7,969
3
V
REF
(V)/R
SET
(
)
Compensation pin. T his is a compensation pin for the internal reference amplifier. A 0.1
μ
F ceramic capacitor
must be connected between COMP and V
AA
.
Voltage reference input. An external 1.23 V voltage reference must be connected to this pin. T he use of an exter-
nal resistor divider network is not recommended. A 0.1
μ
F decoupling ceramic capacitor should be connected be-
tween V
REF
and V
AA
.
Analog power supply (5 V
±
5%). All V
AA
pins on the ADV7128 must be connected.
Ground. All GND pins must be connected.
D0–D9
I
OUT
R
SET
COMP
V
REF
V
AA
GND