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參數(shù)資料
| 型號： | ADV7123KSTZ50 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC VIDEO 3-CH 50MHZ 48LQFP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1 |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 3 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 30mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 6 電流，單極 |
| 采樣率（每秒）： | 50M |
| 產(chǎn)品目錄頁面： | 786 (CN2011-ZH PDF) |
ADV7123
Rev. D | Page 19 of 24
Figure 23 shows the video waveforms associated with the three
RGB outputs driving the doubly terminated 75 Ω load of Figure 24.
As well as the gray scale levels, black level to white level, Figure 23
also shows the contributions of SYNC and BLANK for the
ADV7123. These control inputs add appropriately weighted
currents to the analog outputs, producing the specific output
level requirements for video applications.
details how
the
SYNC and BLANK inputs modify the output levels.
GRAY SCALE OPERATION
The ADV7123 can be used for standalone, gray scale (mono-
chrome), or composite video applications (that is, only one
channel used for video information). Any one of the three
channels, red, green, or blue, can be used to input the digital
video data. The two unused video data channels should be tied
to Logic 0. The unused analog outputs should be terminated
with the same load as that for the used channel; that is, if the
red channel is used and IOR is terminated with a doubly
terminated 75 Ω load (37.5 Ω), IOB and IOG should be
terminated with 37.5 Ω resistors (see Figure 26).
R0
R9
G0
ADV7123
G9
B0
B9
IOR
IOG
37.5
DOUBLY
TERMINATED
7.5
LOAD
VIDEO
OUTPUT
37.5
IOB
GND
0
02
15
-0
26
Figure 26. Input and Output Connections for Standalone Gray Scale or
Composite Video
VIDEO OUTPUT BUFFERS
The ADV7123 is specified to drive transmission line loads. The
analog output configuration to drive such loads is described in
the Analog Outputs section and illustrated in Figure 27. However,
in some applications it may be required to drive long transmis-
sion line cable lengths. Cable lengths greater than 10 meters can
attenuate and distort high frequency analog output pulses. The
inclusion of output buffers compensates for some cable distortion.
Buffers with large full power bandwidths and gains between
two and four are required. These buffers also need to be able to
supply sufficient current over the complete output voltage swing.
Analog Devices produces a range of suitable op amps for such
AD848 series of monolithic op amps. In very high frequency
applications (80 MHz), the AD8061 is recommended. More
information on line driver buffering circuits is given in the
relevant op amp data sheets.
Use of buffer amplifiers also allows implementation of other
video standards besides RS-343A and RS-170. Altering the gain
components of the buffer circuit results in any desired video level.
3
6
2
ZL = 75
(MONITOR)
Z0 = 75
Z2
Z1
+VS
–VS
0.1F
75
(CABLE)
GAIN (G) = 1 +
DACs
IOR, IOG, IOB
ZS = 75
(SOURCE
TERMINATION)
AD848
7
4
Z1
Z2
00
21
5-
0
27
Figure 27. AD848 As an Output Buffer
PCB LAYOUT CONSIDERATIONS
The ADV7123 is optimally designed for lowest noise perfor-
mance, both radiated and conducted noise. To complement the
excellent noise performance of the ADV7123, it is imperative
that great care be given to the PCB layout. Figure 28 shows a
recommended connection diagram for the ADV7123.
The layout should be optimized for lowest noise on the
ADV7123 power and ground lines. This can be achieved by
shielding the digital inputs and providing good decoupling.
Shorten the lead length between groups of VAA and GND pins
to minimize inductive ringing.
It is recommended to use a 4-layer printed circuit board with a
single ground plane. The ground and power planes should
separate the signal trace layer and the solder side layer. Noise
on the analog power plane can be further reduced by using
multiple decoupling capacitors (see Figure 28). Optimum
performance is achieved by using 0.1 μF and 0.01 μF ceramic
capacitors. Individually decouple each VAA pin to ground by
placing the capacitors as close as possible to the device with the
capacitor leads as short as possible, thus minimizing lead
inductance. It is important to note that while the ADV7123
contains circuitry to reject power supply noise, this rejection
decreases with frequency. If a high frequency switching power
supply is used, pay close attention to reducing power supply
noise. A dc power supply filter (Murata BNX002) provides EMI
suppression between the switching power supply and the main
PCB. Alternatively, consideration can be given to using a 3-
terminal voltage regulator.
DIGITAL SIGNAL INTERCONNECT
Isolate the digital signal lines to the ADV7123 as much as
possible from the analog outputs and other analog circuitry.
Digital signal lines should not overlay the analog power plane.
Due to the high clock rates used, long clock lines to the
ADV7123 should be avoided to minimize noise pickup.
Connect any active pull-up termination resistors for the digital
inputs to the regular PCB power plane (VCC) and not the analog
power plane.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7123KSTZ50 | 制造商:Analog Devices 功能描述:IC DAC 10BIT 330MSPS LQFP-48 |
| ADV7123SCP170EP-RL | 功能描述:視頻 IC 5V supply only up to 140MHz IC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| ADV7125 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS, 330 MHz Triple 8-Bit High Speed Video DAC |
| ADV7125_11 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS, 330 MHz Triple 8-Bit High Speed Video DAC |
| ADV7125BCPZ170 | 功能描述:IC DAC VIDEO 3CH 330MHZ 48VFQFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 設(shè)置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
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