Table 9. Typical Video Output Truth Table (RSET = 530 Ω," />
參數(shù)資料
型號(hào)： ADV7123KSTZ50
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/24頁(yè)
文件大?。?/td> 0K
描述： IC DAC VIDEO 3-CH 50MHZ 48LQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 10
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 3
電壓電源： 單電源
功率耗散（最大）： 30mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤
輸出數(shù)目和類型： 6 電流，單極
采樣率（每秒）： 50M
產(chǎn)品目錄頁(yè)面： 786 (CN2011-ZH PDF)
ADV7123
Rev. D | Page 18 of 24
Table 9. Typical Video Output Truth Table (RSET = 530 Ω, RLOAD = 37.5 Ω)
Video Output Level
IOG (mA)
IOR/IOB (mA)
SYNC
BLANK
DAC Input Data
White Level
26.0
0
18.67
0
1
0x3FFH
Video
Video + 7.2
18.67 Video
Video
18.67 Video
1
Data
Video to BLANK
Video
18.67 Video
Video
18.67 Video
0
1
Data
Black Level
7.2
18.67
0
18.67
1
0x000H
Black to BLANK
0
18.67
0
18.67
0
1
0x000H
BLANK Level
7.2
18.67
0
18.67
1
0
0xXXXH (don’t care)
SYNC Level
0
18.67
0
18.67
0
0xXXXH (don’t care)
VIDEO SYNCHRONIZATION AND CONTROL
The ADV7123 has a single composite sync (SYNC) input
control. Many graphics processors and CRT controllers have the
ability of generating horizontal sync (HSYNC), vertical sync
(VSYNC), and composite SYNC.
In a graphics system that does not automatically generate a
composite SYNC signal, the inclusion of some additional logic
circuitry enables the generation of a composite SYNC signal.
The sync current is internally connected directly to the IOG
output, thus encoding video synchronization information onto
the green video channel. If it is not required to encode sync
information onto the ADV7123, the SYNC input should be tied
to logic low.
REFERENCE INPUT
The ADV7123 contains an on-board voltage reference. The VREF
pin is normally terminated to VAA through a 0.1 μF capacitor.
Alternatively, the part can, if required, be overdriven by an
external 1.23 V reference (AD1580).
A resistance, RSET, connected between the RSET pin and GND,
determines the amplitude of the output video level according to
IOG (mA) = 11,445 × VREF (V)/RSET (Ω)
(1)
IOR, IOB (mA) = 7989.6 × VREF (V)/RSET (Ω)
(2)
Equation 1 applies to the ADV7123 only, when SYNC is being
used. If SYNC is not being encoded onto the green channel,
Equation 1 is similar to Equation 2.
Using a variable value of RSET allows for accurate adjustment of
the analog output video levels. Use of a fixed 560 Ω RSET resistor
yields the analog output levels quoted in the Specifications section.
These values typically correspond to the RS-343A video wave-
form values, as shown in Figure 23.
DACs
The ADV7123 contains three matched 10-bit DACs. The DACs
are designed using an advanced, high speed, segmented architec-
ture. The bit currents corresponding to each digital input are
routed to either the analog output (bit = 1) or GND (bit = 0)
by a sophisticated decoding scheme. Because all this circuitry is
on one monolithic device, matching between the three DACs is
optimized. As well as matching, the use of identical current
sources in a monolithic design guarantees monotonicity and
low glitch. The on-board operational amplifier stabilizes the
full-scale output current against temperature and power supply
variations.
ANALOG OUTPUTS
The ADV7123 has three analog outputs, corresponding to the
red, green, and blue video signals.
The red, green, and blue analog outputs of the ADV7123 are
high impedance current sources. Each one of these three RGB
current outputs is capable of directly driving a 37.5 Ω load, such
as a doubly terminated 75 Ω coaxial cable. Figure 24 shows
the required configuration for each of the three RGB outputs
connected into a doubly terminated 75 Ω load. This arrangement
develops RS-343A video output voltage levels across a 75 Ω
monitor.
A suggested method of driving RS-170 video levels into a 75 Ω
monitor is shown in Figure 25. The output current levels of the
DACs remain unchanged, but the source termination resistance,
ZS, on each of the three DACs is increased from 75 Ω to 150 Ω.
IOR, IOG, IOB
ZS = 75
(SOURCE
TERMINATION)
TERMINATION REPEATED THREE TIMES
FOR RED, GREEN, AND BLUE DACs
ZL = 75
(MONITOR)
Z0 = 75
(CABLE)
DACs
00
21
5-
02
4
Figure 24. Analog Output Termination for RS-343A
IOR, IOG, IOB
ZS = 150
(SOURCE
TERMINATION)
TERMINATION REPEATED THREE TIMES
FOR RED, GREEN, AND BLUE DACs
ZL = 75
(MONITOR)
Z0 = 75
(CABLE)
DACs
00
21
5-
02
5
Figure 25. Analog Output Termination for RS-170
More detailed information regarding load terminations for
various output configurations, including RS-343A and RS-170,
is available in the AN-205 Application Note, Video Formats and
Required Load Terminations, available from Analog Devices, at
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