參數(shù)資料
型號(hào): ADUM3200ARZ
廠商: ANALOG DEVICES INC
元件分類: 模擬信號(hào)調(diào)理
英文描述: Dual-Channel, Digital Isolators, Enhanced System-Level ESD Reliability
中文描述: SPECIALTY ANALOG CIRCUIT, PDSO8
封裝: ROHS COMPLIANT, MS-012AA, SOIC-8
文件頁(yè)數(shù): 6/20頁(yè)
文件大小: 222K
代理商: ADUM3200ARZ
ADuM3200/ADuM3201
Parameter
ADuM320xBR
Minimum Pulse Width
2
Maximum Data Rate
3
Propagation Delay
4
Pulse-Width Distortion, |t
PLH
t
PHL
|
4
Change vs. Temperature
Propagation Delay Skew
5
Channel-to-Channel Matching,
Codirectional Channels
6
Channel-to-Channel Matching,
Opposing Directional Channels
6
Output Rise/Fall Time (10% to 90%)
ADuM320xCR
Minimum Pulse Width
2
Maximum Data Rate
3
Propagation Delay
4
Pulse-Width Distortion, |t
PLH
t
PHL
|
4
Change vs. Temperature
Propagation Delay Skew
5
Channel-to-Channel Matching,
Codirectional Channels
6
Channel-to-Channel Matching,
Opposing Directional Channels
6
Output Rise/Fall Time (10% to 90%)
For All Models
Common Mode Transient Immunity
at Logic High Output
7
Common Mode Transient Immunity
at Logic Low Output
7
Refresh Rate
Input Dynamic Supply Current, per Channel
8
Output Dynamic Supply Current, per Channel
8
1
The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11
for total I
DD1
and I
DD2
supply currents as a function of data rate for ADuM3200 and ADuM3201 channel configurations.
2
The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
4
t
PHL
propagation delay is measured from the 50% level of the falling edge of the V
Ix
signal to the 50% level of the falling edge of the V
Ox
signal. t
PLH
propagation delay is
measured from the 50% level of the rising edge of the V
Ix
signal to the 50% level of the rising edge of the V
Ox
signal.
5
t
PSK
is the magnitude of the worst-case difference in t
PHL
and/or t
PLH
that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
CM
H
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V
DD2
. CM
L
is the maximum common-mode voltage slew rate
that can be sustained while maintaining V
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for
information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply
current for a given data rate.
Rev. 0 | Page 6 of 20
Symbol
PW
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD
Min
10
20
Typ
5
Max
100
60
3
22
3
Unit
ns
Mbps
ns
ns
ps/°C
ns
ns
Test Conditions
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
t
PSKOD
22
ns
C
L
= 15 pF, CMOS signal levels
t
R
/t
F
PW
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD
25
20
3.0
20
50
5
40
55
3
16
3
ns
ns
Mbps
ns
ns
ps/°C
ns
ns
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
t
PSKOD
16
ns
C
L
= 15 pF, CMOS signal levels
t
R
/t
F
|CM
H
|
25
3.0
35
ns
kV/μs
C
L
= 15 pF, CMOS signal levels
V
Ix
= V
DD1
, V
DD2
, V
CM
= 1000 V,
transient magnitude = 800 V
V
Ix
= 0 V, V
CM
= 1000 V,
transient magnitude = 800 V
|CM
L
|
25
35
kV/μs
f
r
I
DDI (D)
I
DDO (D)
1.1
0.10
0.03
Mbps
mA/Mbps
mA/Mbps
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ADUM3200ARZ-RL7 Dual-Channel, Digital Isolators, Enhanced System-Level ESD Reliability
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