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參數(shù)資料
| 型號： | ADUM3100BRZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Digital Isolator, Enhanced System-Level ESD Reliability |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO8 |
| 封裝： | ROHS COMPLIANT, MS-012AA, SOIC-8 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 289K |
| 代理商： | ADUM3100BRZ |
ADuM3100
Rev. A | Page 14 of 16
INPUT RISE TIME (10%–90%, ns)
4
1
P
Δ
L
2
0
3
4
8
9
10
3
1
5V INPUT SIGNAL
2
5
6
7
3.3V INPUT SIGNAL
0
Figure 15. Typical Propagation Delay Change due to
Input Rise Time Variation (for V
DD1
= 3.3 V and 5 V)
INPUT RISE TIME (10%–90%, ns)
0
1
P
Δ
H
–2
–4
3
4
8
9
10
–1
–3
2
5
6
7
0
5V INPUT SIGNAL
3.3V INPUT SIGNAL
Figure 16. Typical Propagation Delay Change due to
Input Fall Time Variation (for V
DD1
= 3.3 V and 5 V)
The impact of the slower input edge rates can also affect the
measured pulse-width distortion as based on the input 50%
level. This impact can either increase or decrease the apparent
pulse-width distortion depending on the relative magnitudes of
t
PHL
, t
PLH
, and PWD. The case of interest here is the condition
that leads to the largest increase in pulse-width distortion. The
change in this case is given by
Δ
PWD
= PWD
′
PWD = Δ
LH
Δ
HL
=
(t/0.8 V
1
)(V V
ITH (L-H)
V
ITH (H-L)
),(
for t
=
t
r
=
t
f
)
where:
PWD =
|
t
PLH
t
PHL
|
PWD
′
=
|
t
′
PLH
t
′
PHL
|
This adjustment in pulse-width distortion is plotted as a
function of input rise/fall time in Figure 17.
INPUT RISE/FALL TIME (10%–90%, ns)
6
1
P
P
0
3
4
8
9
10
2
5
6
7
5
4
3
2
1
0
3.3V INPUT SIGNAL
5V INPUT SIGNAL
Figure 17. Typical Pulse-Width Distortion Adjustment due to
Input Rise/Fall Time Variation (at V
DD1
= 3.3 V and 5 V)
METHOD OF OPERATION, DC CORRECTNESS, AND
MAGNETIC FIELD IMMUNITY
Referring to Figure 1, the two coils act as a pulse transformer.
Positive and negative logic transitions at the isolator input
cause narrow (2 ns) pulses to be sent via the transformer to the
decoder. The decoder is bistable and therefore either set or reset
by the pulses indicating input logic transitions. In the absence
of logic transitions at the input for more than 2 μs, a periodic
update pulse of the appropriate polarity is sent to ensure dc
correctness at the output. If the decoder does not receive any of
these update pulses for more than approximately 5 μs, the input
side is assumed to be unpowered or nonfunctional, in which
case the isolator output is forced to a logic high state by the
watchdog timer circuit.
The limitation on the ADuM3100 magnetic field immunity
is set by the condition in which induced voltage in the
transformer receiving coil is sufficiently large to either falsely
set or reset the decoder. The analysis that follows defines the
conditions under which this can occur. The ADuM3100 3.3 V
operating condition is examined because it represents the most
susceptible mode of operation.
The pulses at the transformer output are greater than 1.0 V in
amplitude. The decoder has sensing thresholds at about 0.5 V,
therefore establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
given by
V
= (dβ/
dt
) ∑π
r
n
2
,
n
= 1, 2, . . . ,
N
where:
β = magnetic flux density (gauss).
N
= number of turns in receiving coil.
r
n
= radius of
nth
turn in receiving coil (cm).
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