參數(shù)資料
型號： ADUC7061BCPZ32
廠商： Analog Devices Inc
文件頁數(shù)： 108/108頁
文件大?。?/td> 0K
描述： IC MCU 16/32BIT 32KB 32LFCSP
產品培訓模塊： Weigh Scale Introduction
產品變化通告： ADuC7060/1 Idd Specification Change 01/Feb/2010
設計資源： USB Based Temperature Monitor Using ADuC7061 and an External RTD (CN0075)
4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145)
標準包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 10MHz
連通性： I²C，SPI，UART/USART
外圍設備： POR，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 8
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 1K x 32
電壓 - 電源 (Vcc/Vdd)： 2.375 V ~ 2.625 V
數(shù)據(jù)轉換器： A/D 5x24b，8x24b，D/A 1x14b
振蕩器型： 內部
工作溫度： -40°C ~ 125°C
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
包裝： 管件
產品目錄頁面： 739 (CN2011-ZH PDF)
Data Sheet
ADuC7060/ADuC7061
Rev. D | Page 99 of 108
Table 109. SPICON MMR Bit Designations
Bit
Name
Description
15:14
SPIMDE
SPI IRQ mode bits. These bits are configured when transmit/receive interrupts occur in a transfer.
[00] = transmit interrupt occurs when 1 byte has been transferred. Receive interrupt occurs when one or more bytes
have been received into the FIFO.
[01] = transmit interrupt occurs when 2 bytes have been transferred. Receive interrupt occurs when two or more
bytes have been received into the FIFO.
[10] = transmit interrupt occurs when 3 bytes have been transferred. Receive interrupt occurs when three or more
bytes have been received into the FIFO.
[11] = transmit interrupt occurs when 4 bytes have been transferred. Receive interrupt occurs when the receive FIFO
is full or 4 bytes are present.
13
SPITFLH
SPI transmit FIFO flush enable bit.
Set this bit to flush the transmit FIFO. This bit does not clear itself and should be toggled if a single flush is required. If
this bit is left high, then either the last transmitted value or 0x00 is transmitted, depending on the SPIZEN bit. Any
writes to the transmit FIFO are ignored while this bit is set.
Clear this bit to disable transmit FIFO flushing.
12
SPIRFLH
SPI receive FIFO flush enable bit.
Set this bit to flush the receive FIFO. This bit does not clear itself and should be toggled if a single flush is required. If
this bit is set, all incoming data is ignored and no interrupts are generated. If set and SPITMDE = 0, a read of the
receive FIFO initiates a transfer.
Clear this bit to disable receive FIFO flushing.
11
SPICONT
Continuous transfer enable.
Set by user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in the
transmit register.
A
SSEE
A
is asserted and remains asserted for the duration of each 8-bit serial transfer until the transmit
register is empty.
Cleared by user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists
in the SPITX register, then a new transfer is initiated after a stall period of one serial clock cycle.
10
SPILP
Loopback enable bit.
Set by user to connect MISO to MOSI and test software.
Cleared by user to be in normal mode.
9
SPIOEN
Slave MISO output enable bit.
Set this bit for MISO to operate as normal.
Clear this bit to disable the output driver on the MISO pin. The MISO pin is open drain when this bit is cleared.
8
SPIROW
SPIRX overflow overwrite enable.
Set by user, the valid data in the receive register is overwritten by the new serial byte received.
Cleared by user, the new serial byte received is discarded.
7
SPIZEN
SPI transmit zeros when transmit FIFO is empty.
Set this bit to transmit 0x00 when there is no valid data in the transmit FIFO.
Clear this bit to transmit the last transmitted value when there is no valid data in the transmit FIFO.
6
SPITMDE
SPI transfer and interrupt mode.
Set by user to initiate transfer with a write to the SPITX register. Interrupt occurs only when the transmit FIFO is empty.
Cleared by user to initiate transfer with a read of the SPI register. Interrupt occurs only when the receive FIFO is full.
5
SPILF
LSB first transfer enable bit.
Set by user, the LSB is transmitted first.
Cleared by user, the MSB is transmitted first.
4
SPIWOM
SPI wired or mode enable bit.
Set to 1 to enable the open-drain data output enable. External pull-ups are required on data out pins.
Clear for normal output levels.
3
SPICPO
Serial clock polarity mode bit.
Set by user, the serial clock idles high.
Cleared by user, the serial clock idles low.
2
SPICPH
Serial clock phase mode bit.
Set by user, the serial clock pulses at the beginning of each serial bit transfer.
Cleared by user, the serial clock pulses at the end of each serial bit transfer.
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