參數(shù)資料
型號(hào)： ADSP-BF592KCPZ-2
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 26/44頁(yè)
文件大?。?/td> 0K
描述： IC DSP CTRLR 200MHZ 64LFCSP
視頻文件： Blackfin? BF592 Introduction
特色產(chǎn)品： Blackfin Embedded Processor
標(biāo)準(zhǔn)包裝： 1
系列： Blackfin®
類型： 定點(diǎn)
接口： I²C，I²S，IrDA，PPI，SPI，SPORT，UART
時(shí)鐘速率： 200MHz
非易失內(nèi)存： ROM（64 kB）
芯片上RAM： 64kB
電壓 - 輸入/輸出： 1.8V，2.5V，3.3V
電壓 - 核心： 1.29V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤(pán)
Rev. B
|
Page 32 of 44
|
July 2013
Serial Peripheral Interface (SPI) Port—Slave Timing
Table 27 and Figure 20 describe SPI port slave operations.
Table 27. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
VDDEXT
1.8V Nominal
VDDEXT
2.5 V/3.3V Nominal
Min
Max
Min
Max
Unit
Timing Requirements
tSPICHS
Serial Clock High Period
2 × tSCLK – 1.5
ns
tSPICLS
Serial Clock Low Period
2 × tSCLK – 1.5
ns
tSPICLK
Serial Clock Period
4 × tSCLK
ns
tHDS
Last SCK Edge to SPI_SS Not Asserted
2 × tSCLK – 1.5
ns
tSPITDS
Sequential Transfer Delay
2 × tSCLK – 1.5
ns
tSDSCI
SPI_SS Assertion to First SCK Edge
2 × tSCLK – 1.5
ns
tSSPID
Data Input Valid to SCK Edge (Data Input Setup)
1.6
ns
tHSPID
SCK Sampling Edge to Data Input Invalid
2
1.6
ns
Switching Characteristics
tDSOE
SPI_SS Assertion to Data Out Active
0
12
0
10.3
ns
tDSDHI
SPI_SS Deassertion to Data High Impedance
0
11
0
9
ns
tDDSPID
SCK Edge to Data Out Valid (Data Out Delay)
10
ns
tHDSPID
SCK Edge to Data Out Invalid (Data Out Hold)
0
ns
Figure 20. Serial Peripheral Interface (SPI) Port—Slave Timing
tSPICLK
tHDS
tSPITDS
tSDSCI
tSPICLS
tSPICHS
tDSOE
tDDSPID
tDSDHI
tHDSPID
tSSPID
tDSDHI
tHDSPID
tDSOE
tHSPID
tSSPID
tDDSPID
SPIxSS
(INPUT)
SPIxSCK
(INPUT)
SPIxMISO
(OUTPUT)
SPIxMOSI
(INPUT)
SPIxMISO
(OUTPUT)
SPIxMOSI
(INPUT)
CPHA = 1
CPHA = 0
tHSPID
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