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參數(shù)資料
| 型號： | ADSP-BF531SBBC400 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Metal Connector Backshell |
| 中文描述： | 16-BIT, 40 MHz, OTHER DSP, PBGA160 |
| 封裝： | MO-205AE, CSBGA-160 |
| 文件頁數(shù)： | 13/56頁 |
| 文件大?。?/td> | 671K |
| 代理商： | ADSP-BF531SBBC400 |
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ADSP-BF531/ADSP-BF532/ADSP-BF533
Rev. 0
|
Page 13 of 56
|
March 2004
Alternatively, because the ADSP-BF531/2/3 processor includes
an on-chip oscillator circuit, an external crystal may be used.
The crystal should be connected across the CLKIN and XTAL
pins, with two capacitors connected as shown in
Figure 8
.
Capacitor values are dependent on crystal type and should be
specified by the crystal manufacturer. A parallel-resonant,
fundamental frequency, microprocessor-grade crystal should be
used.
As shown in
Figure 9 on Page 13
, the core clock (CCLK) and
system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a user programmable 1x to 63x multiplica-
tion factor (bounded by specified minimum and maximum
VCO frequencies). The default multiplier is 10x, but it can be
modified by a software instruction sequence. On-the-fly fre-
quency changes can be effected by simply writing to the
PLL_DIV register.
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15.
Table 6
illustrates typical system clock ratios.
The maximum frequency of the system clock is f
SCLK
. Note that
the divisor ratio must be chosen to limit the system clock fre-
quency to its maximum of f
SCLK
. The SSEL value can be changed
dynamically without any PLL lock latencies by writing the
appropriate values to the PLL divisor register (PLL_DIV).
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 7
. This programmable core clock capability is useful for
fast core frequency modifications.
BOOTING MODES
The ADSP-BF531/2/3 processor has two mechanisms (listed in
Table 8
) for automatically loading internal L1 instruction mem-
ory after a reset. A third mode is provided to execute from
external memory, bypassing the boot sequence.
Figure 8. External Crystal Connections
Figure 9. Frequency Modification Methods
CLKIN
CLKOUT
XTAL
PLL
0.5
×
- 64
×
÷ 1:15
÷ 1, 2, 4, 8
VCO
SCLK
≤
CCLK
SCLK
≤
133MHZ
CLKIN
“FINE” ADJUSTMENT
REQUIRES PLL SEQUENCING
“COARSE” ADJUSTMENT
ON-THE-FLY
CCLK
SCLK
Table 6. Example System Clock Ratios
Signal Name
SSEL3–0
Divider Ratio
VCO/SCLK
Example Frequency Ratios
(MHz)
VCO
100
400
500
SCLK
100
133
50
0001
0011
1010
1:1
3:1
10:1
Table 7. Core Clock Ratios
Signal Name
CSEL1–0
Divider Ratio
VCO/CCLK
Example Frequency Ratios
VCO
300
300
500
200
CCLK
300
150
125
25
00
01
10
11
1:1
2:1
4:1
8:1
Table 8. Booting Modes
BMODE1–0
00
Description
Execute from 16-Bit External Memory (Bypass
Boot ROM)
Boot from 8-Bit or 16-Bit FLASH
Reserved
Boot from SPI Serial EEPROM (8-, 16-, or 24-Bit
address range)
01
10
11
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| ADSP-BF531SBBCZC74 | 制造商:Analog Devices 功能描述: |
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