參數(shù)資料
型號(hào)： ADSP-21MSP5859
廠商： Analog Devices, Inc.
英文描述： LM101A/LM201A/LM301A Operational Amplifiers; Package: MDIP; No of Pins: 8; Qty per Container: 40; Container: Rail
中文描述： DSP的微機(jī)
文件頁(yè)數(shù)： 21/32頁(yè)
文件大?。?/td> 231K
代理商： ADSP-21MSP5859
ADSP-21mod870
–21–
REV. 0
Parameter
Bus Request–Bus Grant
Timing Requirements
:
t
BH
t
BS
Switching Characteristics
:
t
SD
t
SDB
t
SE
t
SEC
t
SDBH
t
SEH
Min
Max
Unit
BR
Hold after CLKOUT High
1
BR
Setup before CLKOUT Low
1
0.25 t
CK
+ 2
0.25 t
CK
+ 17
ns
ns
CLKOUT High to
xMS
,
RD
,
WR
Disable
xMS
,
RD
,
WR
Disable to
BG
Low
BG
High to
xMS
,
RD
,
WR
Enable
xMS
,
RD
,
WR
Enable to CLKOUT High
xMS
,
RD
,
WR
Disable to
BGH
Low
2
BGH
High to
xMS
,
RD
,
WR
Enable
2
0.25 t
CK
+ 10
ns
ns
ns
ns
ns
ns
0
0
0.25 t
CK
– 4
0
0
NOTES
xMS
=
PMS
,
DMS
,
CMS
,
IOMS
,
BMS
.
1
BR
is an asynchronous signal. If
BR
meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized
on the following cycle. Refer to the
ADSP-2100 Family User’s Manual, Third Edition,
for
BR
/
BG
cycle relationships.
2
BGH
is asserted when the bus is granted and the processor requires control of the bus to continue.
CLKOUT
t
SD
t
SDB
t
SE
t
SEC
t
SDBH
t
SEH
t
BS
BR
t
BH
CLKOUT
PMS
,
DMS
BMS
,
RD
WR
BG
BGH
Figure 23. Bus Request–Bus Grant
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